74F377A Ver la hoja de datos (PDF) - Philips Electronics
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74F377A Datasheet PDF : 10 Pages
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Philips Semiconductors
Octal D-type flip-flop with enable
Product specification
74F377A
FEATURES
• High impedance inputs for reduced loading (20µA in Low and
High states)
• Ideal for addressable register applications
• Enable for address and data synchronization applications
• Eight edge–triggered D–type flip–flops
• Buffered common clock
• See ’F273A for Master Reset version
• See ’F373 for transparent latch version
• See ’F374 for 3–State version
TYPE
74F377A
TYPICAL fMAX
165MHz
DESCRIPTION
The 74F377A has 8 edge-triggered D-type flip-flops with individual D
inputs and Q outputs. The common buffered clock (CP) input loads
all flip-flops simultaneously when the Enable (E) input is Low.
The register is fully edge triggered. The state of each D input, one
set-up time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop’s Q output.
The E input must be stable one setup time prior to the Low-to-High
clock transition for predictable operation.
TYPICAL SUPPLY CURRENT (TOTAL)
29mA
ORDERING INFORMATION
PACKAGES
20–pin plastic DIP
20–pin plastic SOL
COMMERCIAL RANGE
VCC = 5V±10%; Tamb = 0°C to +70°C
N74F377AN
N74F377AD
PKG. DWG. #
SOT146-1
SOT163-1
INPUT AND OUTPUT LOADING AND FAN–OUT TABLE
PINS
DESCRIPTION
D0 – D7
CP
E
Q0 – Q7
Data inputs
Clock pulse input (active rising edge)
Enable input (active–Low)
Data outputs
74F(U.L.)
HIGH/LOW
1.0/0.033
1.0/0.033
1.0/0.033
50/33
LOAD VALUE
HIGH/LOW
20µA/20µA
20µA/20µA
20µA/20µA
1.0mA/20mA
PIN CONFIGURATION
LOGIC SYMBOL
E1
Q0 2
D0 3
D1 4
Q1 5
Q2 6
D2 7
D3 8
Q3 9
GND 10
20 VCC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CP
SF00350
3 4 7 8 13 14 17 18
D0 D1 D2 D3 D4 D5 D6 D7
11
CP
1
E
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
VCC = Pin 20
GND = Pin 10
2 5 6 9 12 15 16 19
SF00351
1996 Mar 12
2
853–0026 16555
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