74ALVC245 Ver la hoja de datos (PDF) - Philips Electronics
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74ALVC245 Datasheet PDF : 13 Pages
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Philips Semiconductors
Octal bus transceiver; 3-state
Product specification
74ALVC245
FEATURES
• Wide supply voltage range from 1.65 to 3.6 V
• Complies with JEDEC standard:
JESD8-7 (1.65 to 1.95 V)
JESD8-5 (2.3 to 2.7 V)
JESD8B/JESD36 (2.7 to 3.6 V).
• 3.6 V tolerant inputs/outputs
• CMOS LOW power consumption
• Direct interface with TTL levels (2.7 to 3.6 V)
• Power-down mode
• Latch-up performance exceeds 250 mA
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
DESCRIPTION
The 74ALVC245 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
The 74ALVC245 is an octal transceiver featuring
non-inverting 3-state bus compatible outputs in both send
and receive directions. The 74ALVC245 features an
output enable input (OE) for easy cascading and
send/receive input (DIR) for direction control. OE controls
the outputs, so that the buses are effectively isolated.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C.
SYMBOL
PARAMETER
tPHL/tPLH
propagation delay inputs An to Bn;
Bn to An
CI
input capacitance
CI/O
input/output capacitance
CPD
power dissipation capacitance per buffer
CONDITIONS
VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ
VCC = 2.5 V; CL = 30 pF; RL = 500 Ω
VCC = 2.7 V; CL = 50 pF; RL = 500 Ω
VCC = 3.3 V; CL = 50 pF; RL = 500 Ω
VCC = 3.3 V; notes 1 and 2
outputs enable
outputs disabled
TYPICAL UNIT
2.7
ns
2.1
ns
3.0
ns
2.3
ns
3.5
pF
3.5
pF
25
pF
1
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
2003 Jul 10
2
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