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74ALVCH16245DGG

2.5V/3.3V 16-bit bus transceiver with direction pin (3-State)

Philips Electronics 

Philips Semiconductors

16-bit bus transceiver with direction pin (3-State)

Product specification

74ALVC16245/

74ALVCH16245

FEATURES

• Wide supply voltage range of 1.2V to 3.6V

• Complies with JEDEC standard no. 8-1A

• CMOS low power consumption

• MULTIBYTETM flow-through standard pin-out architecture

• Low inductance multiple VCC and ground pins for minimum noise

and ground bounce

• Direct interface with TTL levels

• All data inputs have bus hold (74ALVCH16245 only)

• Output drive capability 50Ω transmission lines @ 85°C

• Current drive ±24 mA at 3.0 V

PIN CONFIGURATION

1DIR 1

1B0 2

1B1 3

GND 4

1B2 5

1B3 6

VCC1 7

1B4 8

1B5 9

GND 10

48 1OE

47 1A0

46 1A1

45 GND

44 1A2

43 1A3

42 VCC2

41 1A4

40 1A5

39 GND

DESCRIPTION

The 74ALVC16245(74ALVCH16245) is a 16-bit transceiver featuring

non-inverting 3-State bus compatible outputs in both send and

receive directions.

The 74ALVC16245(74ALVCH16245) features two output enable

(nOE) inputs for easy cascading and two send/receive (nDIR) inputs

for direction control. nOE controls the outputs so that the buses are

effectively isolated. This device can be used as two 8-bit

transceivers or one 16-bit transceiver.

The 74ALVCH16245 has active bus hold circuitry which is provided

to hold unused or floating data inputs at a valid logic level. This

feature eliminates the need for external pull-up or pull-down

resistors.

The 74ALVC16245 has 5V tolerant inputs.

1B6 11

1B7 12

2B0 13

2B1 14

GND 15

2B2 16

2B3 17

VCC1 18

2B4 19

2B5 20

GND 21

2B6 22

2B7 23

38 1A6

37 1A7

36 2A0

35 2A1

34 GND

33 2A2

32 2A3

31 VCC2

30 2A4

29 2A5

28 GND

27 2A6

26 2A7

2DIR 24

25 2OE

QUICK REFERENCE DATA

GND = 0V; Tamb = 25°C; tr = tf ≤ 2.5ns

SYMBOL

PARAMETER

CONDITIONS

SW00198

TYPICAL

tPHL/tPLH

Propagation delay

An to Bn;

Bn to An

VCC = 2.5V, CL = 30pF

VCC = 3.3V, CL = 50pF

1.9

CI

Input capacitance

4.0

CI/O

Input/output capacitance

8.0

CPD

Power dissipation capacitance per buffer

VI = GND to VCC1

Outputs enabled

29

Outputs disabled

5

NOTE:

1. CPD is used to determine the dynamic power dissipation (PD in µW):

PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;

fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of the outputs.

UNIT

ns

pF

pF

pF

ORDERING INFORMATION

PACKAGES

48-Pin Plastic SSOP Type III

48-Pin Plastic TSSOP Type II

48-Pin Plastic SSOP Type III

48-Pin Plastic TSSOP Type II

TEMPERATURE RANGE

–40°C to +85°C

–40°C to +85°C

–40°C to +85°C

–40°C to +85°C

OUTSIDE NORTH AMERICA

74ALVC16245 DL

74ALVC16245 DGG

74ALVCH16245 DL

74ALVCH16245 DGG

NORTH AMERICA

AC16245 DL

AC16245 DGG

ACH16245 DL

ACH16245 DGG

DWG NUMBER

SOT370-1

SOT362-1

SOT370-1

SOT362-1

1998 Jun 29

2

853-2083 19638

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