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74AHCT259PW Datasheet PDF : 17 Pages
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NXP Semiconductors
74AHC259; 74AHCT259
8-bit addressable latch
Table 8. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11.
Symbol Parameter Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ[1] Max Min Max
Min
Max
tpd
propagation MR to Qn; see Figure 8
[3]
delay
VCC = 3.0 V to 3.6 V
CL = 15 pF
-
5.4 10.5 1.0
12.5
1.0
13.5 ns
CL = 50 pF
-
7.0 13.5 1.0
15.5
1.0
17.0 ns
VCC = 4.5 V to 5.5 V
CL = 15 pF
- 3.9 7.0 1.0
8.5
1.0
9.5 ns
CL = 50 pF
-
5.1 9.0 1.0
10.5
1.0
11.5 ns
tW
pulse width LE HIGH or LOW;
see Figure 7
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
MR LOW; see Figure 8
5.0 -
-
5.0
-
5.0
- ns
5.0 -
-
5.0
-
5.0
- ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
tsu
set-up time D, An to LE; see Figure 9
and Figure 10
5.0 -
-
5.0
-
5.0
- ns
5.0 -
-
5.0
-
5.0
- ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
th
hold time D, An to LE; see Figure 9
and Figure 10
4.0 -
-
4.0
-
4.0
- ns
4.0 -
-
4.0
-
4.0
- ns
VCC = 3.0 V to 3.6 V
1.0 -
-
1.0
-
1.0
- ns
VCC = 4.5 V to 5.5 V
1.0 -
-
1.0
-
1.0
- ns
CPD
power
fi = 1 MHz; VI = GND to VCC [4] -
13
-
-
-
-
- pF
dissipation
capacitance
74AHCT259; VCC = 4.5 V to 5.5 V
tpd
propagation D to Qn; see Figure 5
delay
CL = 15 pF
CL = 50 pF
An to Qn; see Figure 6
[2]
- 4.1 7.5 1.0
9.0
1.0
10.0 ns
-
5.4 9.5 1.0
11.0
1.0
12.0 ns
[2]
CL = 15 pF
CL = 50 pF
LE to Qn; see Figure 7
-
5.5 9.5 1.0
11.5
1.0
12.5 ns
-
6.6 12.0 1.0
14.0
1.0
15.5 ns
[2]
CL = 15 pF
CL = 50 pF
MR to Qn; see Figure 8
- 4.3 8.0 1.0
9.5
1.0
10.4 ns
-
5.5 10.0 1.0
12.0
1.0
13.0 ns
[3]
CL = 15 pF
CL = 50 pF
tW
pulse width LE HIGH or LOW;
see Figure 7
- 3.9 7.0 1.0
8.5
1.0
-
5.1 9.0 1.0
10.5
1.0
5.0 -
-
5.0
-
5.0
9.5 ns
11.5 ns
- ns
MR LOW; see Figure 8
5.0 -
-
5.0
-
5.0
- ns
74AHC_AHCT259_2
Product data sheet
Rev. 02 — 15 May 2008
© NXP B.V. 2008. All rights reserved.
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