74AHCT259PW Ver la hoja de datos (PDF) - NXP Semiconductors.
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74AHCT259PW Datasheet PDF : 17 Pages
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NXP Semiconductors
74AHC259; 74AHCT259
8-bit addressable latch
I Input levels:
N For 74AHC259: CMOS level
N For 74AHCT259: TTL level
I ESD protection:
N HBM EIA/JESD22-A114E exceeds 2000 V
N MM EIA/JESD22-A115-A exceeds 200 V
N CDM EIA/JESD22-C101C exceeds 1000 V
I Multiple package options
I Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
74AHC259
74AHC259D
−40 °C to +125 °C SO16
74AHC259PW −40 °C to +125 °C TSSOP16
74AHCT259
74AHCT259D
−40 °C to +125 °C SO16
74AHCT259PW −40 °C to +125 °C TSSOP16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
plastic small outline package; 16 leads;
body width 3.9 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT109-1
SOT403-1
SOT109-1
SOT403-1
4. Functional diagram
14
LE
Q0 4
13 D
Q1 5
Q2 6
Q3 7
1 A0
Q4 9
2 A1
10
Q5
3
A2
11
Q6
12
Q7
MR
15 mna573
Fig 1. Logic symbol
74AHC_AHCT259_2
Product data sheet
13 Z9
15
G8
14
G10
DX
9,10D
4
1
0
1
C10
8R
0
2
3
G
0
7
1
2
5
6
2
7
3
9
4
10
5
11
6
12
7
mna572
Fig 2. IEC logic symbol
Rev. 02 — 15 May 2008
© NXP B.V. 2008. All rights reserved.
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