73S8023C-IM Ver la hoja de datos (PDF) - Teridian Semiconductor Corporation

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73S8023C-IM

Smart Card Interface

Teridian Semiconductor Corporation 

DS_8023C_019

73S8023C Data Sheet

8 Activation and Deactivation

8.1 Activation Sequence (Synchronous Mode)

The 73S8023C smart card interface IC has an internal ~10 ms delay at power-on reset or on application

of VDD > VDDF. No activation is allowed at this time. CMDVCC (edge triggered) must then be set low to

activate the card.

The following steps list the activation sequence and the timing of the card control signals when the

system controller sets CMDVCC low:

1. CMDVCC is set low.

2. Turn on VCC and I/O (AUX1, AUX2) to reception mode at the end of (tACT).

3. RST is a copy of RSTIN and CLK is a copy of STROBE after (t1).

CMDVCC

VCC

IO

RSTIN

RST

STROBE

CLK

tACT

t1

tACT ~= 500µs

t1 > 0.5µs after tACT, RST = RSTIN, CLK = STROBE

Figure 3: Activation Sequence – Synchronous Mode

8.2 Deactivation Sequence (Synchronous Mode)

Deactivation is initiated either by the system controller by setting the CMDVCC high, or automatically in

the event of hardware faults. Hardware faults are over-current, overheating, VDD fault and card extraction

during the session and are indicated to the system controller by the fall of OFF.

The following steps list the deactivation sequence and the timing of the card control signals when the

system controller sets the CMDVCC high or a fault condition sets OFF low:

1. RST goes low at time t1.

2. CLK stops low at time t2.

3. I/O goes low at time t3. Out of reception mode.

4. VCC is shut down at time t4. After a delay t5 (discharge of the VCC capacitor), VCC is low.

Rev. 1.5

11

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