73S8014RT Ver la hoja de datos (PDF) - Teridian Semiconductor Corporation

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componentes Descripción

Fabricante

73S8014RT

Smart Card Interface

Teridian Semiconductor Corporation 

73S8014RT Data Sheet

DS_8014RT_015

Symbol

Parameter

Condition

Min

Interface Requirements – Data Signals: I/O and Host Interfaces: I/OUC.

ISHORTL, ISHORTH, and VINACT requirements do not pertain to I/OUC.

Output level, high (I/OUC)

IOH =0

IOH = -40μA

0.9 VDD

0.75 VDD

VOH

Output level, high (I/O)

IOH =0

IOH = -40μA (VCC =

3/5V), IOH = -20μA

(VCC = 1.8V)

0.9 VCC

0.75 VCC

Output level, low (I/OUC)

IOL=1mA

VOL

Output level, low (I/O)

Vcc = 5V

Vcc = 3V

Vcc = 1.8V

Input level, high

VIH

Input level, high (I/O)

Input level, low

1.8

0.6 VCC

-0.3

VIL

Input level, low (I/O)

Vcc = 5V, 3V

-0.3

Vcc = 1.8V

-0.3

VINACT

ILEAK

IIL

ISHORTL

Output voltage when outside

of session

Input leakage

Input current, low

Short circuit output current

IOL = 0

IOL = 1mA

VIH = VCC

VIL = 0

For output low,

shorted to VCC

through 33 Ω

ISHORTH

Short circuit output current

For output high,

shorted to ground

through 33 Ω

tR, tF

Output rise time, fall times

CL = 80pF, 10% to

90%.

Nom

Max

VDD+0.1

VDD+0.1

VCC+0.1

VCC+0.1

0.3

0.45

0.2

0.15 VCC

VDD + 0.3

VCC+0.30

0.8

0.8

0.2 VCC

0.1

0.3

10

0.65

15

15

100

tIR, tIF

Input rise, fall times

1

RPU

Internal pull-up resistor

Output stable for

>400ns

8

11

14

FDMAX

Maximum data rate

1

TFDIO

TRDIO

Delay, I/O to I/OUC, I/OUC to

I/O, (respectively falling edge

to falling edge and rising

edge to rising edge)

Edge from master to

slave, measured at

50%

60

100

15

200

CIN

Input capacitance

10

Unit

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

μA

mA

mA

mA

ns

μs

kΩ

MHz

ns

ns

pF

10

Rev. 1.0

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