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73M2901CLIGV

V.22bis Single Chip Modem

TDK Corporation 

73M2901CL

V.22bis Single Chip Modem

SPECIFYING A CRYSTAL

The manufacturer of a crystal resonator verifies its

frequency of oscillation in a test set-up, but to

ensure that the same frequency is obtained in the

application, the circuit conditions must be the same.

The TDK 73M2901CL modem requires a parallel

mode (anti-resonant) crystal, the important

specifications of which are as follows:

Mode:

Parallel (anti-resonant)

Frequency:

11.0592 MHz

Frequency tolerance:

±50 ppm at initial temperature.

Temperature drift:

Crystals with low ESRs may oscillate at higher than

specified voltage levels.

RESET

A reset is accomplished by holding the RESET pin

high. To ensure a proper power-on reset, the reset

pin must be held high for a minimum of 3µs. At

power on, the voltage at VPD, VPA, and RESET

must come up at the same time for a proper reset.

The signals '&', &76 and '65 will be held inactive

for 25ms, acknowledging the reset operation, within

a 250ms time window after the reset-triggering

event. The 73M2901CL is ready for operation after

that 250ms window and/or after the signals '&',

&76 and '65 become active.

An additional ±50 ppm over full range.

Load capacitance:

18pF or 20pF

ESR:

75Ω max.

Drive level:

Less than 1mW.

The peak voltage level of the oscillator should be

checked to assure it will not violate the maximum

voltage levels allowed on the oscillator pins. A

resistor in series with the crystal can be used, if

necessary, to reduce the oscillator’s peak voltage

levels.

ASYNCHRONOUS AND SYNCHRONOUS SERIAL

DATA INTERFACE

The serial data interface consists of the TXD and

RXD data paths (LSB shifted in and out first,

respectively); and the TXCLK and RXCLK serial

clock outputs associated with the data pins;

&76/576 flow control; '&', '65 and '75. In

synchronous mode, the data is passed at the bit rate

(tolerance is +1%, -2.5%).

PIN DESCRIPTIONS

POWER PIN DESCRIPTION

PIN

NAME

32 pin

PLCC

32 pin

TQFP

44 pin LQFP TYPE DESCRIPTION

VPA

15

10

16

I Positive analog voltage (Analog supply)

VNA

VPD

21

16

6, 25, 29 2, 20, 25

22

2, 12, 27, 33

I Negative analog voltage (Analog ground)

I Positive digital voltage (Digital supply)

VND

5, 22, 26 1, 17, 22 11, 24, 44, 28

I Negative digital voltage (Digital ground)

ANALOG INTERFACE PIN DESCRIPTION

PIN

NAME

32 pin

PLCC

32 pin

TQFP

44 pin LQFP

RXA

20

15

21

TXAN

16

11

17

TXAP

17

12

18

VBG

19

14

20

VREF

18

13

19

TYPE DESCRIPTION

I Receive Analog input

O Transmit Analog - output

O Transmit Analog + output

Analog Band Gap voltage reference (0.1µF to

O VNA). This pin must not be connected to external

circuitry other than the decoupling capacitor.

O Analog reference voltage (0.1µF to VNA)

3

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