GS881E18AT-250 Ver la hoja de datos (PDF) - Giga Semiconductor
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GS881E18AT-250 Datasheet PDF : 34 Pages
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TQFP Pin Description
Pin Location
37, 36
35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46,
47, 48, 49, 50,
80
63, 62, 59, 58, 57, 56, 53, 52, 51
68, 69, 72, 73, 74, 75, 78, 79, 80
13, 12, 9, 8, 7, 6, 3, 2, 1
18, 19, 22, 23, 24, 25, 28, 29, 30
58, 59, 62, 63, 68, 69, 72, 73, 74
8, 9, 12, 13, 18, 19, 22, 23, 24
51, 52, 53, 56, 57
75, 78, 79,
1, 2, 3, 6, 7,
25, 28, 29, 30, 95, 96, 97
16, 66
87
93, 94
Symbol
A0, A1
A2–A17
A18
DQA1–DQA9
DQB1–DQB9
DQC1–DQC9
DQD1–DQD9
DQA1–DQA9
DQB1–DQB9
NC
NC
BW
BA, BB
95, 96
BC, BD
97
89
88
97
98
86
83
84, 85
64
31
15, 41, 65, 91
5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90
4, 11, 20, 27, 54, 61, 70, 77
NC
CK
GW
E2
E1
G
ADV
ADSP, ADSC
ZZ
LBO
VDD
VSS
VDDQ
Type
I
I
I
I/O
I/O
—
—
I
I
I
—
I
I
I
I
I
I
I
I
I
I
I
I
Preliminary
GS881E18/36AT-250/225/200/166/150/133
Description
Address field LSBs and Address Counter preset Inputs
Address Inputs
Address Inputs (x18 versions)
Data Input and Output pins (x36 Version)
Data Input and Output pins (x18 Version)
No Connect (x18 Version)
No Connect
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQA, DQB Data I/Os; active low
Byte Write Enable for DQC, DQD Data I/’s; active low
(x36 Version)
No Connect (x36 Version)
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active high
Chip Enable; active low
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Linear Burst Order mode; active low
Core power supply
I/O and Core Ground
Output driver power supply
Rev: 1.01 3/2002
4/34
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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