5962R9582401QQC Ver la hoja de datos (PDF) - Intersil

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5962R9582401QQC

Radiation Hardened 8-Bit CMOS Microprocessor

Intersil 

HS-80C85RH

Waveforms (Continued)

T2

T2

THOLD

THOLD

T1

CLK

HOLD

HLDA

tHDS

BUS

(ADDRESS, CONTROLS)

tHDH tHACK

tHABF

tHABE

FIGURE 5. HOLD

CLK

T1

T2

tLCK

TWAIT

T3

T3

tCA

A8-15

AD0-AD7

ALE

RD/INTA

READY

ADDRESS

ADDRESS

tLL

tLA

tAL

tLC

tLRY

tAC

tARY

tAD

tAFR

tLDR

tRD

tCC

tRYS tRYH

tRYS tRYH

tRDH

DATA IN

tRAE

tCL

NOTE: READY must remain stable during setup and hold times.

FIGURE 6. READ OPERATION WITH WAIT CYCLE (TYPICAL) - SAME READY TIMING APPLIES TO WRITE

T1

T2

T3

T4

T5

T6 THOLD T1

T2

A8-15

A0-7

CALL INST.

BUS FLOATING (NOTE)

RD

INTR

tINS

INTR

tINH

HOLD

tHDH

HLDA tHDS

tHACK

tHABE

tHABF

NOTE: IO/M is also floating during this time.

FIGURE 7. INTERRUPT AND HOLD

6

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