DSP56F827FG80 Ver la hoja de datos (PDF) - Motorola => Freescale
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DSP56F827FG80 Datasheet PDF : 52 Pages
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Freescale Semiconductor, Inc.
Signals and Package Information
Table 3. 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)
Signal Name Pin No.
Type
Description
DS
(PCS1)
RD
WR
TA0
17
Output
Data Memory Select—DS is asserted low for external Data memory
access. This pin can also be programmed as a programmable chip
select.
15
Output
Read Enable—RD is asserted during external memory read cycles.
When RD is asserted low, pins D0–D15 become inputs and an external
device is enabled onto the device data bus. When RD is deasserted
high, the external data is latched inside the device. When RD is
asserted, it qualifies the A0–A15, PS, and DS pins. RD can be
connected directly to the OE pin of a Static RAM or ROM.
16
Output
Write Enable—WR is asserted during external memory write cycles.
When WR is asserted low, pins D0–D15 become outputs and the
device puts data on the bus. When WR is deasserted high, the external
data is latched inside the external device. When WR is asserted, it
qualifies the A0–A15, PS, and DS pins. WR can be connected directly
to the WE pin of a Static RAM.
112 Input/Output TA0–3—Timer A Channels 0, 1, 2, and 3
(GPIOF0)
TA1
(GPIOF1)
TA2
(GPIOF2)
TA3
(GPIOF3)
TCK
TMS
TDI
TDO
TRST
DE
Input/Output Port F GPIO—These four General Purpose I/O (GPIO) pins can be
individually programmed as input or output.
111
After reset, the default state is Quad Timer.
110
109
44
Input
Test Clock Input—This input pin provides a gated clock to synchronize
(Schmitt) the test logic and shift serial data to the JTAG/OnCE port. The pin is
connected internally to a pull-down resistor.
46
Input
Test Mode Select Input—This input pin is used to sequence the JTAG
(Schmitt) TAP controller’s state machine. It is sampled on the rising edge of TCK
and has an on-chip pull-up resistor.
48
Input
Test Data Input—This input pin provides a serial input data stream to
(Schmitt) the JTAG/OnCE port. It is sampled on the rising edge of TCK and has
an on-chip pull-up resistor.
47
Input/Output Test Data Output—This tri-statable output pin provides a serial output
data stream from the JTAG/OnCE port. It is driven in the Shift-IR and
Shift-DR controller states, and changes on the falling edge of TCK.
45
Input
Test Reset—As an input, a low signal on this pin provides a reset
(Schmitt) signal to the JTAG TAP controller. To ensure complete hardware reset,
TRST should be asserted whenever RESET is asserted. The only
exception occurs in a debugging environment when a hardware device
reset is required and it is necessary not to reset the JTAG/OnCE
module. In this case, assert RESET, but do not assert TRST. TRST
must always be asserted at power-up.
41
Output
Debug Event—DE provides a low pulse on recognized debug events.
56F827 Technical Data
11
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