AS4LC1M16883C-8 Ver la hoja de datos (PDF) - Austin Semiconductor

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AS4LC1M16883C-8

1 MEG x 16 DRAM

Austin Semiconductor 

AUSTIN SEMICONDUCTOR, INC.

AS4LC1M16 883C

1 MEG x 16 DRAM

PRELIMINARY

EDO PAGE MODE (continued)

?W/E can also perform the function of disabling the output

drivers under certain conditions, as shown in Figure 2.

During an application, if the DQ outputs are wire OR’d,

?O/E must be used to disable idle banks of DRAMs. Alterna-

tively, pulsing ?W/E to the idle banks during ?C?A/S HIGH time

will also High-Z the outputs. Independent of ?O/E control,

the outputs will disable after tOFF, which is referenced

from the rising edge of ?R?A/S or ?C?A/S, whichever occurs last.

RAS

V IH

V IL

CASL/CASH

V

V

IH

IL

,, ,,, ,,,,, ADDR

V

V

IH

IL

,,,,, , , DQ VVIIOOHL

ROW

COLUMN (A)

OPEN

VALID DATA (A)

t WHZ

WE

V IH

V IL

tWPZ

OE

V

V

IH

IL

,,,,,, ,,,,, COLUMN(B)

COLUMN (C)

,, ,,,,, VALIDDATA(B)

t WHZ

INPUT DATA (C)

COLUMN (D)

The DQs go to High-Z if WE falls, and if tWPZ is met,

will remain High-Z until CAS goes LOW with

WE HIGH (i.e., until a READ cycle is initiated).

Figure 2

?W/E CONTROL OF DQs

WE may be used to disable the DQs to prepare

for input data in an EARLY WRITE cycle. The DQs

will remain High-Z until CAS goes LOW with

WE HIGH (i.e., until a READ cycle is initiated).

,,DON’T CARE

,,,,UNDEFINED

AS4LC1M16

REV. 3/97

DS000020

2-95

Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.

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