48SD1616 Ver la hoja de datos (PDF) - MAXWELL TECHNOLOGIES

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48SD1616

256 Mb SDRAM 4-Meg X 16-Bit X 4-Banks

MAXWELL TECHNOLOGIES 

256Mb (4-Meg X 16-Bit X 4-Banks) SDRAM

48SD1616

DQMU/DQML Truth Table

COMMAND

Upper byte (DQ8 to DQ15) write enable/out-

put enable

Lower byte (DQ0 to DQ7) write enable/out-

put enable

Upper byte (DQ8 to DQ15) write inhibit/out-

put disable

Lower byte (DQ0 to DQ7) write inhibit/out-

put disable

SYMBOL

ENBU

ENBL

MASKU

MASKL

CKE=N-1

H

H

H

H

CKE=N

x

x

x

x

Note: H: VIH L: VIL x VIH or VIL

Write: IDID is Needed

Read: IDOD is Needed

The SDRAM can mask input/output data by means of DQMU/DQML.

DQMU

L

x

H

x

DQML

x

L

x

H

DQMU masks the upper byte and DQML masks the lower byte.

During reading, the output buffer is set to Low-Z by setting DQMU/DQML to Low, enabling data output. On

the other hand, when DQMU/DQML is set High, the output buffer becomes High-Z, disabling data output.

During writing, data is written by setting DQMU/DQML to Low. When DQMU/DQML is set to High, the

previous data is held ( the new data is not written). Desired data can be masked during burst read or burst

write by setting DQMU/DQML. For more details, refer to the DQMU/DQML control section of the SDRAM

operating instructions.

01.07.05 REV 4

All data sheets are subject to change without notice 10

©2005 Maxwell Technologies

All rights reserved.

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