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3507 Datasheet PDF : 28 Pages
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LT3507
PIN FUNCTIONS
BOOST1, BOOST2, BOOST3 (Pins 1, 27, 32): The BOOST
pins are used to provide drive voltages, higher than the
input voltage, to the internal bipolar NPN power switches.
These pins must be tied through a diode from VOUT, VIN
or another supply greater than 2.5V.
VIN1 (Pins 2, 3): The VIN1 pins supply power to the internal
switch of the 2.4A regulator and to the LT3507’s internal
reference and start-up circuitry. These pins must be locally
bypassed (Note 6).
VINSW (Pin 4): The VINSW pin is a switched VIN1 for the
user programmable undervoltage and overvoltage detec-
tion. It is connected to VIN1 when any of the RUN pins
are pulled high, and high impedance when all RUN pins
are low or open.
OVLO (Pin 5): The LT3507 goes into overvoltage shutdown
when this pin goes above 1.2V. If unused, the OVLO pin
should be tied to GND.
UVLO (Pin 6): The LT3507 goes into undervoltage shutdown
when this pin drops below 1.2V. If unused, the UVLO pin
should be tied to VINSW.
VC1, VC2, VC3 (Pins 7, 23, 19): The VC pins are the outputs
of the internal error amps. The voltages on these pins
control the peak switch currents. These pins are normally
used to compensate the control loops. Each switching
regulator can be shut down by pulling its respective VC
pin to ground with an NMOS or NPN transistor.
TRK/SS1, TRK/SS2, TRK/SS3, TRK/SS4 (Pins 8, 21, 18,
26): The TRK/SS pins allow a regulator to track the output
of another regulator. When the TRK/SS pin is below 0.8V,
the FB pin regulates to the TRK/SS voltage. This pin can
also be used as a soft-start by connecting a capacitor from
TRK/SS to ground. The TRK/SS pins should be left open
if neither feature is used.
FB1, FB2, FB3 (Pins 9, 22, 20): The FB pins are the nega-
tive inputs of the error amplifiers. The LT3507 regulates
each feedback pin to the lesser of 0.8V or the TRK/SS
pin voltage. Connect the feedback resistor divider taps
to these pins.
PGOOD1, PGOOD2, PGOOD3 (Pins 10, 11, 12): The
PGOOD pins are the open-collector outputs of an internal
comparator. PGOOD remains low until the FB pin is within
10% of the final regulation voltage. As well as indicating
output regulation, the PGOOD pins can sequence the
switching regulators. These pins must be left unconnected
if unused. The PGOOD outputs are valid when VIN is greater
than 3.5V and any of the RUN pins are high. They are not
valid when all RUN pins are low.
RT/SYNC (Pin 13): The RT/SYNC pin requires a resistor
to ground or a clock signal to set the operating frequency
of the LT3507.
RUN1, RUN2, RUN3 (Pins 14, 15, 16): The RUN pins are
used to shut down the individual switching regulators.
When all three RUN pins are low, the LT3507 shuts down
and draws less than 1μA from VIN1.
BIAS (Pin 17): The BIAS pin supplies the current to the
LT3507’s internal regulator. This pin should be tied to the
lowest available voltage source above 3V (either VIN, VOUT
or any other available supply). The LDO pass transistor’s
base current is supplied from the BIAS pin if it is at least
0.8V above the LDO DRIVE output.
DRIVE (Pin 24): The DRIVE pin provides the base drive for
an external NPN transistor used for the LDO regulator.
FB4 (Pin 25): The FB4 pin is the negative input to the LDO
error amplifier. It is regulated to 0.8V through the LDO
feedback resistor divider.
VIN2 (Pins 30, 31)/VIN3 (Pins 35, 36 ): The VIN2 and VIN3
pins supply power to the internal switches of the 1.5A con-
verters. These pins must be locally bypassed (Note 6).
SW1 (Pins 37, 38)/SW2 (Pins 28, 29)/SW3 (Pins 33,
34): The SW pins are the outputs of the internal power
switches. Connect these pins to the inductors and switch-
ing diodes.
Exposed Pad (Pin 39): Ground. The underside Exposed
Pad metal of the package provides both electrical contact
to ground and good thermal contact to the printed circuit
board. The Exposed Pad must be soldered to a grounded
pad on the circuit board for proper operation.
Note 6: VINX pins that are connected together may share a bypass capacitor.
3507f
7

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