TQ6122-D Ver la hoja de datos (PDF) - TriQuint Semiconductor

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TQ6122-D

1 Gigasample/sec, 8-bit Digital-to-Analog Converter

TriQuint Semiconductor 

TQ6122

blanking current would be undesirable. For cases such

as these, the blanking current may be completely

turned off by connecting the BLANK_DISABLE pin to

AGND.

with effective binary weightings from 1/16 of full scale

down to 1/128 of full scale. The blanking bit steers a

current which is nominally 10.4% of the full-scale

amplitude.

Master/Slave Latch With Encode Logic

Current-Source Array

A nine-wide master latch registers the data coming from

the multiplexer and blanking logic. The latch outputs are

then split into two groups. The top three bits are trans-

lated into a seven-level thermometer code by a binary-

to-N-of-seven encoder, while the lower five data bits

and the blanking bit are simply delayed. The seven

encoder outputs and the six delayed data and blanking

bits are re-registered in a slave latch to minimize skew,

which, in turn, reduces the glitch impulse. Latch timing

is set up such that the slave latch is in the “sample” mode

when the input clock is LOW, meaning that the analog

output is updated at the falling edge of the clock.

Current Switches

The thermometer code outputs of the slave latch array

drive seven switches, each of which steers a current

equal to 1/8 of the full-scale step amplitude. The five

encoded data bits, on the other hand, switch currents

The current-source array is the heart of the DAC from

an analog standpoint, and is responsible for generating

the segment, bit, and blanking currents. The maximum

full-scale current IFS (less IBLANK) is about 45 mA,

providing a 1.125 volt maximum swing into the 50-

ohm external load. The blanking current is nominally

10.4% of IFS, corresponding to a 10-unit IRE blanking

interval of 71 mV when the full-scale output is set to

0.679 volt. The IREF current tracks IFS, with a nominal

value of 2.5 mA for IFS = 40 mA (i.e., 6.25% of IFS).

Figure 13 (A) illustrates the basic circuit of the current-

source array, which consists of a set of current sources

ranging from the 5 mA segment currents to the binary-

weighted current sources for the lower-order bits. The

circuit design utilizes source degeneration, averaging,

and linear gradient cancellation techniques to obtain

matching consistent with up to 10-bit linearity.

Figure 13 (A). Current-Source Array Circuit — VSENSE -Based Control Method

VOUT VOUT

BLANK

IREF

2.5 mA

(NOM)

DIFF-PAIR SWITCH

BLANK (TYPICAL, 15 PLACES)

I BLANK

ISEG 1

ISEG 7

IB4

IB3

CASCODES

+

VREF

2W

–

EXT

REF.

0.8 V NOM, VSENSE

FOR 1 V F.S. OUT

RS

3.56W

4W

RS

RS

1.77

2

4W

2W

W

RS

2

RS

2RS

VAA

– 5V

I B0

VBIAS

(INTERNAL)

RLSB

For additional information and latest specifications, see our website: www.triquint.com

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