2SK3204 Ver la hoja de datos (PDF) - NEC => Renesas Technology
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2SK3204 Datasheet PDF : 4 Pages
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2SK3204
• ELECTRICAL CHARACTERISTICS (TA = 25 °C)
PARAMATERS
SYMBOL
TEST CONDITIONS
Drain to Source On-state Resistance
Gate to Source Cut-off Voltage
Forward Transfer Admittance
Drain Leakage Current
Gate to Source Leakage Current
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
RDS(on)1
RDS(on)2
VGS(off)
| yfs |
IDSS
IGSS
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QG
QGS
QGD
VF(S-D)
trr
Qrr
VGS = 10 V, ID = 8 A
VGS = 4 V, ID = 8 A
VDS = 10 V, ID = 1 mA
VDS = 10 V, ID = 8 A
VDS = 60 V, VGS = 0 V
VGS = ±20 V, VDS = 0 V
VDS = 10 V, VGS = 0 V, f = 1 MHz
ID = 8 A, VGS(on) = 10 V, VDD = 30 V,
RG = 10 Ω
ID = 15 A, VDD = 48 V, VGS(on) = 10 V
IF = 15 A, VGS = 0 V
IF = 15 A, VGS = 0 V,
di/dt = 100 A/µs
MIN.
1.0
8.0
TYP.
25
35
1.5
14
940
290
120
17
150
58
52
25
2.9
7.5
0.92
45
81
MAX.
34
50
2.0
10
±10
UNIT
mΩ
mΩ
V
S
µA
µA
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
• TEST CIRCUIT 1 AVALANCHE CAPABILITY
• TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG = 25 Ω
L
PG.
50 Ω
VDD
VGS = 20 → 0 V
IAS
ID
VDD
BVDSS
VDS
Starting Tch
• TEST CIRCUIT 3 GATE CHARGE
D.U.T.
PG.
RG
RG = 10 Ω
VGS
0
τ
τ = 1 µs
Duty Cycle ≤ 1 %
RL
VDD
VGS
VGS
Wave Form
10 %
0
ID
ID
Wave Form
0 10 %
VGS(on)
90 %
ID
90 %
90 %
10 %
td(on)
tr td(off)
tf
ton
toff
D.U.T.
IG = 2 mA
RL
PG.
50 Ω
VDD
2
Data sheet D13796EJ1V0DS00
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