ILC5062AM Ver la hoja de datos (PDF) - Impala Linear Corporation
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ILC5062AM Datasheet PDF : 6 Pages
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SOT-23 Power Supply reset Monitor With Complementary CMOS Output
Functional Description
The following designators 1~6 refer to the timing diagram below.
1. While the input voltage (VIN) is higher than the detect
voltage (VDF), the output voltage at VOUT pin equals the
input voltage at VIN pin.
4. During an increase of the input voltage from the VSS
voltage, VOUT is undefined at the voltage below VMIN.
Exceeding the VMIN level, the ouput stays at the ground
level (VSS) between the minimum operating voltage (VMIN)
and the detect release voltage (VDR).
2. When the input VIN voltage falls lower than VDF, VOUT
drops near ground voltage.
3. If the input voltage decreases below the minimum operat-
ing voltage (VMIN), the VOUT output voltage will be undefined.
5. If the input voltage increases more than VDR, the output
voltage at VOUT pin equals the input voltage at VIN pin.
6. The difference between VDR and VDF is the hysteresis
in the system.
Timing Diagram
INPUT VOLTAGE (VIN)
DETECT RELEASE VOLTAGE (VDR)
6
DETECT FAIL VOLTAGE (VDF)
MINIMUM OPERATING VOLTAGE (VMIN)
GROUND VOLTAGE (VSS)
OUTPUT VOLTAGE (VOUT)
1
2
GROUND VOLTAGE (VSS)
3
4
5
Impala Linear Corporation
ILC5062 1.3
(408) 574-3939 www.impalalinear.com
June 1999 3
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