ML2712CH Ver la hoja de datos (PDF) - Micro Linear Corporation

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componentes Descripción

Fabricante

ML2712CH

2.4GHz RF Transceiver

Micro Linear Corporation 

PRELIMINARY

ML2712

MODES OF OPERATION (CONTINUED)

OVERVIEW OF PLLS

Control words programmed via the Serial Control

Bus set the ML2712 PLL reference frequency

divider,and the 2LO PLL and 1LO PLL signal dividers

division ratios. For illustration a simple PLL is shown

in Figure 7.

TUNING

VOLTAGE

CONTROL

VCO

RF OUT

LOOP

FILTER

DIVIDE PLL

BY P DIVIDER

PHASE

DETECTOR

I

φ

CHARGE

PUMP

REFERENCE

DIVIDER

DIVIDE

BY M

CRYSTAL

OSCILLATOR

REFERENCE

Figure 7. Simple PLL

The simplified signal divide by P ( Figure 7) uses a dual

modulus (or swallow pulse) prescaler system.

Figure 8 shows a dual modulus signal divider. This type of

PLL is able to divide by two integers, N and N+1. ND &

NS, are clocked in parallel by pulses from the prescaler,

which is initially set to N+1. The ND & NS registers are

programmed via the Serial Control Bus. The signal divider

ratio achieved by this system is given by the equation:

The output of the signal divider is compared with the

500 kHz comparison frequency from the reference

divider in the phase detector. In the PLL (Fig. 8) the

tuning voltage to the VCO is adjusted until phase locking

occurs. At this point the VCO frequency in MHz will be

given by the equation:

f = (N ´ ND + NS) ´ (fR/M).

Note that since both PLL signal divider and reference

divider are subject to an extra divide by two stage,

they may be neglected in the equations. However, it

is important to note that the comparison frequency

in MHz in both the 1LO and the 2LO PLL is given by

fC = fR/2M.

DAC AND RSSI COMPARATOR

The DAC can be used to generate a voltage output to

control the transmit power in an external power amplifier

(PA). The DAC and Comparator can also be used to form

an RSSI threshold circuit or an RSSI tracking A/D in

conjunction with external baseband circuits. The DAC is

programmed via the Serial Control Bus using either the

DACEN or the EN control line. The DAC may be

programmed at serial clock rates up to 16MHz.

SLEEP MODE

In SLEEP Mode only the control circuits are active.

These circuits are static CMOS and consume minimal

current when there is no interface activity.

RSD = N ´ ND + NS. ND must be greater than NS.

PRESCALER

FROM

VCO

N/N+1

CLK

IF NS≠0

THEN N+1

ELSE N

NS COUNTER

ND COUNTER

TO PHASE

DETECTOR

NS COUNTER

MODULUS

ND COUNTER

MODULUS

Figure 8. Dual Modulus Signal Divider

January, 2000 PRELIMINARY DATASHEET

11

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