MRFIC2403 Ver la hoja de datos (PDF) - Motorola => Freescale
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MRFIC2403 Datasheet PDF : 6 Pages
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TYPICAL CHARACTERISTICS
25
70
26
23
POUT
60
25
TA = – 30°C
21
24
50
25°C
EFFICIENCY
23
19
40
85°C
22
17
30
f = 2.45 GHz
21
15
13
VDD = 5.0 Vdc
VG1 = –1.0 Vdc
20
20
VG2 = –2.0 Vdc
10
19
Pin = +4.0 dBm
VDD = 5.0 Vdc
VG1 = –1.0 Vdc
VG2 = –2.0 Vdc
11
0
–10 – 8 – 6 – 4 – 2 0
2
4
6
PIN, INPUT POWER (dBm)
18
2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0
f, FREQUENCY (GHz)
Figure 2. Output Power and Efficiency versus
Input Power
25
Figure 3. Output Power versus Frequency
20
15
10
f = 2.45 GHz
Pin = +4.0 dBm
5
VDD = 5.0 Vdc
VG1 = –1.0 Vdc
0
VG2 = –2.0 Vdc
–5
0
1
2
3
4
5
PCNTRL, (VOLTS)
Figure 4. Output Power versus PCNTRL Voltage
DESIGN AND APPLICATIONS INFORMATION
The MRFIC2403 is a two–stage power amplifier designed
using Motorola’s MAFET planar, refractory gate MESFET IC
process. The RF MESFETs are power, depletion mode
devices and, therefore, require negative bias on the MESFET
gates. For class B operation, –1.0 Vdc is applied to VG1 and
–2.0 Vdc is applied to VG2. Class A biasing will yield slightly
higher gain and 1.0 dB compression point and can be accom-
plished by adjusting the bias on VG1 for IDQ1 = 24 mA and
VG2 for IDQ2 = 96 mA. Where negative voltages are not
already available, Motorola’s MC33128 Power Management
IC can produce –2.5 Vdc from a single positive supply.
The device is capable of better than +23 dBm saturated
output power in the 2.4 to 2.5 GHz ISM band with the output
matching circuit shown in Figure 1. The device can be
operated at other frequencies in the 2.0 GHz to 3.0 GHz
range with this circuit but performance can be improved
with tuning for the specific frequency of use. Input match-
ing is provided on chip. This circuit provides the best gain,
saturated output power and efficiency tradeoff. Saturated
operation has the advantage of best efficiency with less
variation in performance over frequency and temperature.
Operation in saturation is acceptable for constant enve-
lope modulation schemes such as 2 and 4 level FM as spe-
cified for frequency hopping (FHSS) radios in the proposed
IEEE 802.11 PHY layer specification. For direct sequence
(DSSS) IEEE 802.11 operation, where differential binary
phase shift keying (DBPSK) and differential quadrature
phase shift keying (DQPSK) are specified, the amplifier will
have to be “backed off” from saturation by 5.0 dB or more to
avoid spectral regrowth. Care must be taken in the layout of
the circuit and controlled impedance lines must be used at
the RF pins. Capacitive bypassing as shown in the Applica-
tions Circuit must be implemented as close to the chip as
possible to avoid amplifier instability. Additionally, the supply
voltage should be supported by sufficient “stiffening” capaci-
tance, typically electrolytic or tantalum bypass capacitors, to
eliminate noise from digital circuits.
Output power control is accomplished by varying the volt-
age on the PCNTRL pin. 0 Vdc gives minimum output and
reduces the current drawn by the amplifier to the quiescent
value. The amplifier can be put into “sleep” mode by
decreasing the voltage on the gate bias pins to –3.0 Vdc and
the current drain is reduced to a few hundred microamps.
EVALUATION BOARDS
Evaluation boards are available for RF Monolithic Inte-
grated Circuits by adding a “TF” suffix to the device type.
For a complete list of currently available boards and ones
in development for newly introduced poduct, please con-
tact your local Motorola Distributor or Sales Office.
MOTOROLA RF DEVICE DATA
MRFIC2403
5
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