HUFA76504DK8 Ver la hoja de datos (PDF) - Fairchild Semiconductor
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HUFA76504DK8
Fairchild Semiconductor
HUFA76504DK8 Datasheet PDF : 13 Pages
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HUFA76504DK8
SABER Electrical Model
REV 18 January 2001
template HUFA76504dk8 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (is = 3.1e-13, n1 = 1.03, rs = 4.2e-2, trs1 = 3e-4, trs2 = 1.3e-6, cjo = 6.82e-10, tt = 3.38e-8, m = 0.8, xti = 4)
dp..model dbreakmod = (rs = 1.65, trs1 = 1e-3, trs2 = -9e-6)
dp..model dplcapmod = (cjo = 1.7e-10, isl = 10e-30, n1 = 10, m = 0.85)
m..model mmedmod = (type=_n, vto = 2.2, kp = 1.1, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 2.56, kp = 18, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.94, kp = 0.04, is = 1e-30, tox = 1, rs = .1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4, voff = -1)
DPLCAP
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -1, voff = -4)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0.5)
10
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -0.5)
c.ca n12 n8 = 2.5e-10
c.cb n15 n14 = 3e-10
RSLC2
5
RSLC1
51
ISCL
RDBREAK
72
LDRAIN
DRAIN
2
RLDRAIN
RDBODY
c.cin n6 n8 = 2.6e-10
dp.dbody n7 n71 = model=dbodymod
dp.dbreak n72 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 4.21e-10
l.lsource n3 n7 = 1.28e-10
-
ESG
6
8
+
LGATE
EVTEMP
GATE
1
RGATE + 18 - 6
9
20 22
RLGATE
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
EVTHRES
+ 19 -
8
CIN
50
RDRAIN
16
21
DBREAK
11
MWEAK
MMED
MSTRO
8
EBREAK
+
17
18
-
7
71
DBODY
LSOURCE
SOURCE
3
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
RSOURCE
RLSOURCE
res.rbreak n17 n18 = 1, tc1 = 1.12e-3, tc2 = -3e-7
res.rdrain n50 n16 = 1.1e-1, tc1 = 9e-3, tc2 = 2e-5
res.rgate n9 n20 = 5.74e1
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 42.1
res.rlsource n3 n7 = 12.8
res.rslc1 n5 n51 = 1e-6, tc1 = 2.8e-3, tc2 = 1.9e-5
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 5.72e-2, tc1 = 1e-3, tc2 = 1e-6
res.rvtemp n18 n19 = 1, tc1 = -1.5e-3, tc2 = 1e-6
S1A
12 13
8
S2A
14
15
13
S1B
S2B
CA
13
CB
+
+ 14
EGS
6
8
-
EDS
5
8
-
RBREAK
17
18
RVTEMP
19
IT
-
VBAT
+
8
22
res.rvthres n22 n8 = 1, tc1 = -2e-3, tc2 = -3e-6
RVTHRES
spe.ebreak n11 n7 n17 n18 = 100.6
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/12))** 3.7))
}
}
©2001 Fairchild Semiconductor Corporation
Rev. A, June 4, 2001
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