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28F008SA-L

8-MBIT (1 MBIT x 8) FLASHFILE™ MEMORY

Intel 

28F008SA-L

Data Protection

Depending on the application the system designer

may choose to make the VPP power supply switcha-

ble (available only when memory byte writes block

erases are required) or hardwired to VPPH When

VPP e VPPL memory contents cannot be altered

The 28F008SA-L Command User Interface architec-

ture provides protection from unwanted byte write or

block erase operations even when high voltage is

applied to VPP Additionally all functions are dis-

abled whenever VCC is below the write lockout volt-

age VLKO or when RP is at VIL The 28F008SA-L

accommodates either design practice and encour-

ages optimization of the processor-memory inter-

face

The two-step byte write block erase Command User

Interface write sequence provides additional soft-

ware write protection

The first task is to write the appropriate read mode

command to the Command User Interface (array In-

telligent Identifier or Status Register) The

28F008SA-L automatically resets to Read Array

mode upon initial device powerup or after exit from

deep powerdown The 28F008SA-L has four control

pins two of which must be logically active to obtain

data at the outputs Chip Enable (CE ) is the device

selection control and when active enables the se-

lected memory device Output Enable (OE ) is the

data input output (DQ0 – DQ7) direction control and

when active drives data from the selected memory

onto the I O bus RP and WE must also be at

VIH Figure 10 illustrates read bus cycle waveforms

Output Disable

With OE at a logic-high level (VIH) the device out-

puts are disabled Output pins (DQ0 – DQ7) are

placed in a high-impedance state

BUS OPERATION

Flash memory reads erases and writes in-system

via the local CPU All bus cycles to or from the flash

memory conform to standard microprocessor bus

cycles

Read

The 28F008SA-L has three read modes The memo-

ry can be read from any of its blocks and informa-

tion can be read from the Intelligent Identifier or

Status Register VPP can be at either VPPL or VPPH

Standby

CE at a logic-high level (VIH) places the

28F008SA-L in standby mode Standby operation

disables much of the 28F008SA-L’s circuitry and

substantially reduces device power consumption

The outputs (DQ0 – DQ7) are placed in a high-impe-

dence state independent of the status of OE If the

28F008SA-L is deselected during block erase or

byte write the device will continue functioning and

consuming normal active power until the operation

completes

Mode

Read

Output Disable

Standby

Deep PowerDown

Intelligent Identifier (Mfr)

Intelligent Identifier (Device)

Write

Table 2 Bus Operations

Notes RP CE OE WE

123

VIH VIL VIL VIH

123

VIH VIL VIH VIH

123

VIH VIH

X

X

12

VIL

X

X

X

12

VIH VIL VIL VIH

12

VIH VIL VIL VIH

1 2 3 4 5 VIH VIL VIH VIL

A0 VPP DQ0–7 RY BY

X X DOUT

X

X X High Z

X

X X High Z

X

X X High Z

VIL X

VIH X

XX

89H

A1H

DIN

VOH

VOH

VOH

X

NOTES

1 Refer to DC Characteristics When VPP e VPPL memory contents can be read but not written or erased

2 X can be VIL or VIH for control pins and addresses and VPPL or VPPH for VPP See DC Characteristics for VPPL and VPPH

voltages

3 RY BY is VOL when the Write State Machine is executing internal block erase or byte write algorithms It is VOH when

the WSM is not busy in Erase Suspend mode or deep powerdown mode

4 Command writes involving block erase or byte write are only successfully executed when VPP e VPPH

5 Refer to Table 3 for valid DIN during a write operation

9

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