28F008SA-L Ver la hoja de datos (PDF) - Intel

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28F008SA-L

8-MBIT (1 MBIT x 8) FLASHFILE™ MEMORY

Intel 

28F008SA-L

Deep Power-Down

The 28F008SA-L offers a deep power-down feature

entered when RP is at VIL Current draw thru VCC

is 0 20 mA typical in deep powerdown mode with

current draw through VPP typically 0 1 mA During

read modes RP -low deselects the memory

places output drivers in a high-impedence state and

turns off all internal circuits The 28F008SA-L re-

quires time tPHQV (see AC Characteristics-Read-

Only Operations) after return from powerdown until

initial memory access outputs are valid After this

wakeup interval normal operation is restored The

Command User Interface is reset to Read Array and

the upper 5 bits of the Status Register are cleared to

value 10000 upon return to normal operation

During block erase or byte write modes RP low

will abort either operation Memory contents of the

block being altered are no longer valid as the data

will be partially written or erased Time tPHWL after

RP goes to logic-high (VIH) is required before an-

other command can be written

This use of RP during system reset is important

with automated write erase devices When the sys-

tem come out of reset it expects to read from the

flash memory Automated flash memories provide

status information when accessed during write

erase modes If a CPU reset occurs with no flash

memory reset proper CPU initialization would not

occur because the flash memory would be providing

the status information instead of array data Intel’s

Flash Memories allow proper CPU initialization fol-

lowing a system reset through the use of the RP

input In this application RP is controlled by the

same RESET signal that resets the system CPU

Intelligent Identifier Operation

The Intelligent Identifier operation outputs the manu-

facturer code 89H and the device code A2H for

the 28F008SA-L The system CPU can then auto-

matically match the device with its proper block

erase and byte write algorithms

The manufacturer- and device-codes are read via

the Command User Interface Following a write of

90H to the Command User Interface a read from

address location 00000H outputs the manufacturer

code (89H) A read from address 00001H outputs

the device code (A2H) It is not necessary to have

high voltage applied to VPP to read the Intelligent

Identifiers from the Command User Interface

Table 3 Command Definitions

Command

Bus

Cycles Notes

First Bus Cycle

Second Bus Cycle

Req’d

Operation Address Data Operation Address Data

Read Array Reset

1

1

Write

X FFH

Intelligent Identifier

3 2 3 4 Write

X

90H Read

IA

IID

Read Status Register

2

3

Write

X

70H Read

X SRD

Clear Status Register

1

Write

X

50H

Erase Setup Erase Confirm

2

2

Write

BA 20H Write

BA D0H

Erase Suspend Erase Resume

2

Write

X B0H Write

X D0H

Byte Write Setup Write

2 2 3 5 Write

WA 40H Write

WA WD

Alternate Byte Write Setup Write 2 2 3 5 Write

WA 10H Write

WA WD

NOTES

1 Bus operations are defined in Table 2

2 IA e Identifier Address 00H for manufacturer code 01H for device code

BA e Address within the block being erased

WA e Address of memory location to be written

3 SRD e Data read from Status Register See Table 4 for a description of the Status Register bits

WD e Data to be written at location WA Data is latched on the rising edge of WE

IID e Data read from Intelligent Identifiers

4 Following the Intelligent Identifier command two read operations access manufacture and device codes

5 Either 40H or 10H are recognized by the WSM as the Byte Write Setup command

6 Commands other than those shown above are reserved by Intel for future device implementations and should not be

used

10

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