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21555

Non-Transparent PCI-to-PCI Bridge

Intel 

1.0

1.1

Non-Transparent PPB

Introduction

Intel’s 21555 is a PCI peripheral device that performs PCI bridging functions for embedded and

intelligent I/O applications. The 21555 has a 64-bit primary interface, a 64-bit secondary interface,

and 66-MHz capability. The 21554 a related PCI peripheral device, has a 64-bit primary interface,

a 64-bit secondary interface, and 33-MHz capability.”

The 21555 is a “non-transparent” PCI-to-PCI bridge that acts as a gateway to an intelligent

subsystem. It allows a local processor to independently configure and control the local subsystem.

The 21555 implements an I2O message unit that enables any local processor to function as an

intelligent I/O processor (IOP) in an I2O-capable system. Because the 21555 is architecture

independent, it works with any host and local processors that support a PCI bus. This architecture

independence enables vendors to leverage existing investments while moving products to PCI

technology.

Unlike a transparent PCI-to-PCI bridge, the 21555 is specifically designed to bridge between two

processor domains. The processor domain on the primary interface of the 21555 is also referred to

as the host domain, and its processor is the host processor. The secondary bus interfaces to the local

domain and the local processor. Special features include support of independent primary and

secondary PCI clocks, independent primary and secondary address spaces, and address translation

between the primary (host) and secondary (local) domains.

The 21555 enables add-in card vendors to present to the host system a higher level of abstraction

than is possible with a transparent PCI-to-PCI bridge. The 21555 uses a Type 0 configuration

header, which presents the entire subsystem as a single “device” to the host processor. This allows

loading of a single device driver for the entire subsystem, and independent local processor

initialization and control of the subsystem devices. Because the 21555 uses a Type 0 configuration

header, it does not require hierarchical PCI-to-PCI bridge configuration code.

The 21555 forwards transactions between the primary and secondary PCI buses as does a

transparent PCI-to-PCI bridge. In contrast to a transparent PCI-to-PCI bridge, however, the 21555

can translate the address of a forwarded transaction from a system address to a local address, or

vice versa. This mechanism allows the 21555 to hide subsystem resources from the host processor

and to resolve any resource conflicts that may exist between the host and local subsystems.

The 21555 operates at 3.3 V and is also 5.0-V I/O tolerant. Adapter cards designed using the 21555

can be keyed as universal, thus permitting use in either a 5-V or 3-V slot.

Comparing 21555 and Standard PCI-to-PCI Bridge

The 21555 is functionally similar to a standard PCI-to-PCI bridge (PPB) in that both provide a

connection path between devices attached to two independent PCI buses. A 21555 and a PPB allow

the electrical loading of devices on one PCI bus to be isolated from the other bus while permitting

concurrent operation on both buses. Because the PCI Local Bus Specification restricts PCI option

cards to a single electrical load, the ability of PPBs and the 21555 to spawn PCI buses enables the

design of multi device PCI option cards. The key difference between a PPB and the 21555 is that

the presence of a PPB in a connection path between the host processor and a device is transparent

to devices and device drivers, while the presence of the 21555 is not. This difference enables the

21555 to provide features that better support the use of intelligent controllers in the subsystem.

Datasheet

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