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A28F200BX-B

2-MBIT (128K x 16, 256K x 8) BOOT BLOCK FLASH MEMORY FAMILY

Intel 

A28F200BX-T B

Intel’s 2-Mbit Flash Memory Family is an extension of the Boot Block Architecture which includes block-selec-

tive erasure automated write and erase operations and standard microprocessor interface The 2 Mbit Flash

Memory Family enhances the Boot Block Architecture by adding more density and blocks x8 x16 input out-

put control very high speed low power an industry standard ROM compatible pinout The 2-Mbit flash family

allows for an easy upgrade to Intel’s 4-Mbit Boot Block Flash Memory Family

The Intel A28F200BX-T B are 16-bit wide flash memory offerings optimized to meet the rigorous environmen-

tal requirements of Automotive Applications These high density flash memories provide user selectable bus

operation for either 8-bit or 16-bit applications The A28F200BX-T and A28F200BX-B are 2 097 152-bit non-

volatile memories organized as either 262 144 bytes or 131 072 words of information They are offered in 44-

Lead plastic SOP packages The x8 x16 pinout conforms to the industry standard ROM EPROM pinout Read

and Write Characteristics are guaranteed over the ambient temperature range of b40 C to a125 C

These devices use an integrated Command User Interface (CUI) and Write State Machine (WSM) for simplified

word byte write and block erasure The A28F200BX-T provides block locations compatible with Intel’s

MCS-186 family 80286 i386TM i486TM i860TM and 80960CA microprocessors The A28F200BX-B provides

compatibility with Intel’s 80960KX and 80960SX families as well as other embedded microprocessors

The boot block includes a data protection feature to protect the boot code in critical applications With a

maximum access time of 90 ns these 2 Mbit flash devices are very high performance memories which

interface at zero-wait-state to a wide range of microprocessors and microcontrollers

Manufactured on Intel’s 0 8 micron ETOXTM III process the 2-Mbit flash memory family provides world class

quality reliability and cost-effectiveness at the 2-Mbit density level

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