A28F200BX-B Ver la hoja de datos (PDF) - Intel
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A28F200BX-B Datasheet PDF : 33 Pages
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A28F200BX-T B
AC CHARACTERISTICS For WE -Controlled Write Operations(1)
Versions(4)
Symbol
Parameter
Notes
tAVAV
tWC
Write Cycle Time
tPHWL
tPS
RP High Recovery to
WE Going Low
tELWL
tCS
CE Setup to WE Going Low
tPHHWH
tPHS
RP VHH Setup to WE Going High
68
tVPWH
tVPS
VPP Setup to WE Going High
58
tAVWH
tAS
Address Setup to WE Going High
3
tDVWH
tDS
Data Setup to WE Going High
4
tWLWH
tWP
WE Pulse Width
tWHDX
tDH
Data Hold from WE High
4
tWHAX
tAH
Address Hold from WE High
3
tWHEH
tCH
CE Hold from WE High
tWHWL
tWPH WE Pulse Width High
tWHQV1
Duration of Word Byte
25
Write Operation
tWHQV2
tWHQV3
Duration of Erase Operation (Boot)
Duration of Erase
Operation (Parameter)
256
25
tWHQV4
tQWL
tQVPH
tPHBR
tVPH
tPHH
Duration of Erase Operation (Main)
VPP Hold from Valid SRD
RP VHH Hold from Valid SRD
Boot-Block Relock Delay
256
58
68
78
A28F200BX-90(9)
Min
Max
90
210
0
100
100
60
60
60
0
10
10
30
7
04
04
07
0
0
100
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
s
s
s
ns
ns
ns
NOTES
1 Read timing characteristics during write and erase operations are the same as during read-only operations Refer to AC
Characteristics during Read Mode
2 The on-chip WSM completely automates program erase operations program erase algorithms are now controlled inter-
nally which includes verify and margining operations
3 Refer to command definition table for valid AIN
4 Refer to command definition table for valid DIN
5 Program Erase durations are measured to valid SRD data (successful operation SR 7e1)
6 For Boot Block Program Erase RP should be held at VHH until operation completes successfully
7 Time tPHBR is required for successful relocking of the Boot Block
8 Sampled but not 100% tested
9 See Standard Test Configuration
28
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