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28F002BX-B

2-MBIT (128K x 16, 256K x 8) BOOT BLOCK FLASH MEMORY FAMILY

Intel 

28F200BX-T B 28F002BX-T B

1 5 Pin Descriptions for the x8 x16 28F200BX

Symbol

A0 – A16

A9

DQ0 – DQ7

DQ8 – DQ15

CE

RP

OE

WE

BYTE

VPP

VCC

GND

NC

DU

Type

I

I

IO

IO

I

I

I

I

I

Name and Function

ADDRESS INPUTS for memory addresses Addresses are internally latched

during a write cycle

ADDRESS INPUT When A9 is at 12V the signature mode is accessed During this

mode A0 decodes between the manufacturer and device ID’s When BYTE is at

a logic low only the lower byte of the signatures are read DQ15 Ab1 is a don’t

care in the signature mode when BYTE is low

DATA INPUTS OUTPUTS Inputs array data on the second CE and WE cycle

during a program command Inputs commands to the Command User Interface

when CE and WE are active Data is internally latched during the write and

program cycles Outputs array Intelligent Identifier and Status Register data The

data pins float to tri-state when the chip is deselected or the outputs are disabled

DATA INPUTS OUTPUTS Inputs array data on the second CE and WE cycle

during a program command Data is internally latched during the write and program

cycles Outputs array data The data pins float to tri-state when the chip is

deselected or the outputs are disabled as in the byte-wide mode (BYTE e‘‘0’’)

In the byte-wide mode DQ15 Ab1 becomes the lowest order address for data

output on DQ0 – DQ7

CHIP ENABLE Activates the device’s control logic input buffers decoders and

sense amplifiers CE is active low CE high deselects the memory device and

reduces power consumption to standby levels If CE and RP are high but not

at a CMOS high level the standby current will increase due to current flow through

the CE and RP input stages

RESET DEEP POWER-DOWN Provides three-state control Puts the device in

deep power-down mode Locks the boot block from program erase

When RP is at logic high level and equals 6 5V maximum the boot block is

locked and cannot be programmed or erased

When RP e 11 4V minimum the boot block is unlocked and can be programmed

or erased

When RP is at a logic low level the boot block is locked the deep power-down

mode is enabled and the WSM is reset preventing any blocks from being

programmed or erased therefore providing data protection during power

transitions When RP transitions from logic low to logic high the flash memory

enters the read array mode

OUTPUT ENABLE Gates the device’s outputs through the data buffers during a

read cycle OE is active low

WRITE ENABLE Controls writes to the Command Register and array blocks

WE is active low Addresses and data are latched on the rising edge of the WE

pulse

BYTE ENABLE Controls whether the device operates in the byte-wide mode

(x8) or the word-wide mode (x16) BYTE pin must be controlled at CMOS levels

to meet 100 mA CMOS current in the standby mode BYTE e ‘‘0’’ enables the

byte-wide mode where data is read and programmed on DQ0 – DQ7 and

DQ15 Ab1 becomes the lowest order address that decodes between the upper

and lower byte DQ8 – DQ14 are tri-stated during the byte-wide mode

BYTE e ‘‘1’’ enables the word-wide mode where data is read and programmed

on DQ0 – DQ15

PROGRAM ERASE POWER SUPPLY For erasing memory array blocks or

programming data in each block

Note VPP k VPPLMAX memory contents cannot be altered

DEVICE POWER SUPPLY (5V g10% 5V g 5%)

GROUND For all internal circuitry

NO CONNECT Pin may be driven or left floating

DON’T USE PIN Pin should not be connected to anything

8

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