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28F002BC

2-MBIT (256K X 8) BOOT BLOCK FLASH MEMORY

Intel 

E

28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY

Start

Write 20H and

Block Address

Write D0H and

Block Address

Read Status Register

0

SR.7 =

Suspend Erase

Loop

No

Yes

Suspend

Erase

1

Full Status

Check if Desired

Bus

Command

Operation

Comments

Write

Write

Erase Setup

Erase

Confirm

Data = 20H

Addr = Within Block to Be Erased

Data = D0H

Addr = Within Block to Be Erased

Read

Status Register Data

Toggle CE# or OE# to Update

Status Register

Standby

Check SR.7

1 = WSM Ready

0 = WSM Busy

Repeat for subsequent block erasures.

Full Status Check can be done after each block erase, or after a

sequence of block erasures.

Write FFH after the last operation to reset device to read array mode.

Block Erase

Complete

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

1

SR.3 =

0

1

SR.4,5 =

0

1

SR.5 =

0

Block Erase

Successful

VPP Range Error

Command Sequence

Error

Block Erase

Error

Bus

Operation

Standby

Standby

Standby

Command

Comments

Check SR.3

1 = VPP Low Detect

Check SR.4,5

Both 1 = Command

Sequence Error

Check SR.5

1 = Block Erase Error

SR.3 MUST be cleared, if set during an erase attempt, before further

attempts are allowed by the Write State Machine.

SR.5 is only cleared by the Clear Status Register command, in

cases where multiple blocks are erase before full status is checked.

If error is detected, clear the status register before attempting

retry or other error recovery.

0578_07

Figure 8. Automated Block Erase Flowchart

PRELIMINARY

21

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