EM84520EP Ver la hoja de datos (PDF) - ELAN Microelectronics

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EM84520EP

2-in-one scrolling mouse controller

ELAN Microelectronics 

C) PS/2 mouse Data Transmission:

EM84520

2-IN-ONE SCROLLING MOUSE CONTROLLER

Preliminary

a). EM84520 generates the clocking signal when sending data to and receiving data from the system.

b). The system requests EM84520 receive system data output by forcing the DATA line to an inactive level

and allowing CLK line to go to an active level.

c). Data transmission frame:

Bit

Function

1

Start bit ( always 0 )

2-9

Data bits ( D0 - D7 )

10

Parity bit ( odd parity )

11

Stop bit ( always 1 )

d). Data Output ( data from EM84520 to system ):

If CLK is low ( inhibit status ) , data is no transmission.

If CLK is high and DATA is low ( request-to-send ), data is updated. Data is received from the system

and no transmission are started by EM84520 until CLK and DATA both high. If CLK and DATA both

are high, the transmission is ready. DATA is valid prior to the falling edge of CLK and beyond the rising edge

of CLK. During transmission, EM84520 check for line contention by checking for an inactive level on CLK

at intervals not to exceed 100u sec. Contention occurs when the system lowers CLK to inhibit EM84520

output after EM84520 has started a transmission. If this occurs before the rising edge of the tenth clock,

EM84520 internal store its data in its buffer and returns DATA and CLK to an active level. If the contention

does not occur by the tenth clock, the transmission is complete.

Following a transmission, the system inhibits EM84520 by holding CLK low until it can service the input

or until the system receives a request to send a response from EM84520.

e). Data Input ( from system to EM84520 ):

The system first check if EM84520 is transmitting data. If EM84520 is transmitting, the system can override

the output forcing CLK to an inactive level prior to the tenth clock. If EM84520 transmission is beyond

the tenth clock, the system receives the data. If EM84520 is not transmitting or if the system choose to

override the output, the system force CLK to an inactive level for a period of not less than 100µ sec while

preparing for output. When the system is ready to output start bit (0), it allows CLK go to active level. If

request-to-send is detected, EM84520 clocks 11 bits. Following the tenth clock EM84520 checks for

an active level on the DATA line, and if found, force DATA low , and clock once more. If occurs framing

error, EM84520 continue to clock until DATA is high, then clocks the line control bit and request a

Resend. When the system sends out a command or data transmission that requires a response, the system

waits for EM84520 to response before sending its next output.

D). PS/2 Mouse Error Handling:

a). A Resend command ( FE ) following receipt of an invalid input or any input with incorrect parity.

b). If two invalid input are received in succession, an error code of hex (FC) is send to the system.

* This specification are subject to be changed without notice.

6.28.1999 5

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