TS4851 Ver la hoja de datos (PDF) - STMicroelectronics

Número de pieza

componentes Descripción

Fabricante

TS4851

Mono 1W Speaker and Stereo 160mW Headset BTL Drivers with Digital Volume Control

STMicroelectronics 

SPI Bus Interface

TS4851

2 SPI Bus Interface

Table 2. Pin description

Pin

DATA

CLK

ENB

Functional Description

This is the serial data input pin.

This is the clock input pin.

This is the SPI enable pin active at high level.

2.1 Description of SPI operation

The serial data bits are organized into a field containing 8 bits of data as shown in Table 3. The DATA 0 to

DATA 2 bits determine the output mode of the TS4851 as shown in Table 2. The DATA 3 to DATA 7 bits

determine the gain level setting as illustrated by Table 3. For each SPI transfer, the data bits are written to

the DATA pin with the least significant bit (LSB) first. All serial data are sampled at the rising edge of the

CLK signal. Once all the data bits have been sampled, ENB transitions from logic-high to logic low to

complete the SPI sequence. All 8 bits must be received before any data latch can occur. Any excess CLK

and DATA transitions will be ignored after the height rising clock edge has occurred. For any data

sequence longer than 8 bits, only the first 8 bits will get loaded into the shift register and the rest of the bits

will be disregarded.

Table 3. Bit allocation

LSB

MSB

DATA

DATA 0

DATA 1

DATA 2

DATA 3

DATA 4

DATA 5

DATA 6

DATA 7

MODES

Mode 1

Mode 2

Mode 3

gain 1

gain 2

gain 3

gain 4

gain 5

Table 4. Output mode selection: G from -34.5dB to +12dB (by steps of 1.5dB)

Output

Mode #

DATA 2

DATA 1

DATA 0

SPKERout1

0

0

0

0

SD

1

0

0

1

6dBxP

2

0

1

0

SD

3

0

1

1

Gx(R+L)

4

1

0

0

SD

5

1

0

1

Gx(R+L)

+6dBxP

6

1

1

0

SD

7

1

1

1

6dBxP

1) SD = Shutdown Mode, P = Phone in Input, R = Rin input and L = Lin input

Rout

SD

SD

0dBxP

SD

GxR

SD

GxR+0dBxP

GxR+0dBxP

Lout

SD

SD

0dBxP

SD

GxL

SD

GxL+0dBxP

GxL+0dBxP

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