PDM41028 Ver la hoja de datos (PDF) - Paradigm Technology
Número de pieza
componentes Descripción
Fabricante
PDM41028 Datasheet PDF : 8 Pages
| |||
PDM41028
AC Electrical Characteristics
Description
WRITE Cycle
-10(7)
-12(7)
-15
1
Sym Min. Max. Min. Max. Min. Max. Units
WRITE Cycle time
tWC
10
12
15
ns
Chip enable active time
tCW
10
10
11
ns
2
Address Valid to end of write
tAW
10
10
11
ns
Address setup time
tAS
0
0
0
ns
Address hold from end of write
tAH
0
0
0
ns
Write pulse width
tWP1
9
10
11
ns
3
Write pulse width
tWP2
10
11
12
ns
Data setup time
Data hold time
tDS
7
7
7
ns
tDH
0
0
0
ns
4
Write disable to output in low Z(1,3)
tLZWE
0
0
0
ns
Write enable to output in high Z(1,3) tHZWE
7
7
7 ns
SHADED AREA = PRELIMINARY DATA
5
Notes referenced are after Data Retention Table
Low VCC Data Retention Waveform
6
Data Retention Mode
V CC
4.5V
VDR
4.5V
7
t CDR
tR
VIH
CE VIL
VDR
8
DON'T CARE
Data Retention Electrical Characteristics (LA Version Only)
9
Symbol Parameter
Test Conditions
Min. Typ. Max. Unit
VDR
ICCDR
VCC for Retention Data
Data Retention Current
CE ≥ VCC – 0.2V
VIN ≥ VCC – 0.2V
or ≤ 0.2V
2
VCC = 2V
—
VCC = 3V
—
—
—
10 —
V
500 µA
—
750 µA
tCDR
tR(3)
Chip Deselect to Data Retention Time
Operation Recovery Time
0
tRC
—
—
11 —
ns
—
ns
NOTES: (For three previous Electrical Characteristics tables)
1. The parameter is tested with CL = 5 pF as shown in Figure 2. Transition is measured ±200 mV from steady state voltage.
2. At any given temperature and voltage condition, tHZCE is less than tLZCE.
3. This parameter is sampled.
4. WE is high for a READ cycle.
12
5. The device is continuously selected. Chip Enable is held in its active state.
6. The address is valid prior to or coincident with the latest occuring Chip Enable.
7. Vcc = 5V ± 5%.
Rev. 2.2 - 4/29/98
7
Share Link: 