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MT28F160A3

1 MEG x 16 ENHANCED BOOT BLOCK FLASH MEMORY

Micron Technology 

ADVANCE

1 MEG x 16

ENHANCED BOOT BLOCK FLASH MEMORY

MEMORY ORGANIZATION

The MT28F160A3 memory array is segmented into 31

blocks of 32K words, along with eight 4K-word parameter

blocks. The device is available with block architecture

mapped in either of the two configurations: the boot

blocks located at the top or at the bottom of the memory

array, as required by different microprocessors. The

MT28F160A3 top boot configuration with the blocks and

address ranges is shown in Figure 1 and the bottom boot

configuration in Figure 2.

The boot blocks are used to store key system data and

are seldom changed during normal operation. When the

WP# is at VIL , the contents of the boot block cannot be

erased or reprogrammed. The boot block contents can be

changed only through proper command sequences when

WP# is HIGH (see Table 5).

COMMAND STATE MACHINE

Commands are issued to the command state ma-

chine (CSM) using standard microprocessor write tim-

ings. The CSM acts as an interface between the external

microprocessor and the internal write state machine

(WSM). The available commands are listed in Table 2,

and the descriptions of these commands are shown in

Table 3. Program and erase algorithms are automated by

an on-chip WSM. Once a valid program/erase command

sequence is entered, the WSM executes the appropriate

algorithm, which generates the necessary timing signals

to control the device internally to accomplish the re-

quested operation. A command is valid only if the exact

sequence of WRITEs is completed. After the WSM com-

pletes its task, the WSM status bit (SR7) is set to a logic

HIGH level (1), allowing the CSM to respond to the full

command set again.

OPERATION

Device operations are selected by entering standard

JEDEC 8-bit command codes with conventional micro-

processor timings into an on-chip CSM through I/Os

DQ0-DQ7. When the device is powered up, internal reset

circuitry initializes the chip to a read array mode of op-

eration. Changing the mode of operation requires that a

command code be entered into the CSM. The on-chip

status register allows the progress of various operations

to be monitored. The status register is interrogated by

entering a READ STATUS REGISTER command onto the

CSM (cycle 1) and reading the register data on I/Os DQ0-

DQ7 (cycle 2). Status register bits SR0-SR7 correspond to

DQ0-DQ7 (see Table 3).

Table 2

Command State Machine Codes for

Device Mode Selection

COMMAND

DQ0-DQ7

10h/40h

20h

50h

70h

90h

B0h

D0h

FFh

60h, 0Fh, AFh

CODE ON

DEVICE MODE

Write setup/alternate write setup

Block erase setup

Clear status register

Read status register

Identify device

Program/erase suspend

Program/erase resume

Erase confirm

Read array

Reserved

1 Meg x 16 Enhanced Boot Block Flash Memory

MT28F160A3_3.p65 – Rev. 3, Pub. 8/01

7

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2001, Micron Technology, Inc.

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