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100329A

Low Power Octal ECL/TTL Bidirectional Translator with Register

Fairchild Semiconductor 

Test Circuitry (ECL-to-TTL)

Note: RT = 50Ω termination resistive load. When an input or output is being monitored by a scope, RTis supplied by the scope’s 50Ω input resistance. When

an input or output is not being monitored, an external 50Ω resistance must be applied to serve as RT.

Note: The TTL 3-STATE pull-up switch is connected to +7V only for ZL and LZ tests.

Note: TTL and ECL force signals are brought to the DUT via 50Ω coax lines.

Note: VTTL is decoupled to ground with 0.1 µF, VEE is decoupled to ground with 0.01 µF and VCC is connected to ground.

FIGURE 3. ECL-to-TTL AC Test Circuit

Switching Waveforms (ECL-to-TTL)

Note: DIR is LOW, OE is HIGH

FIGURE 4. ECL-to-TTL Transition—Propagation Delay and Transition Times

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