HYB314405BJL-60 Ver la hoja de datos (PDF) - Siemens AG

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Fabricante

HYB314405BJL-60

1M x 4-Bit Dynamic RAM (Hyper Page Mode (EDO) version)

Siemens AG 

HYB 314405BJ/BJL-50/-60/-70

3.3V 1M x 4 EDO - DRAM

DC Characteristics (cont’d)

TA = 0 to 70 ˚C, VSS = 0 V, VCC = 3.3 V ± 0.3 V, tT = 2 ns

Parameter

Symbol

Limit Values

min.

max.

Standby VCC supply current

(RAS = CAS = WE = VCC – 0.2 V)

Average VCC supply current during

CAS before RAS refresh mode

-50 version

-60 version

-70 version

ICC5

–

ICC6

1

200

–

70

–

60

–

55

For Low Power Version only:

ICC7

–

250

Battery backup current (average power supply

current in battery backup mode):

(CAS = CAS before RAS cycling or 0.2 V,

WE = VCC – 0.2 V or 0.2 V,

A0 to A10 = VCC – 0.2 V or 0.2 V;

DI = VCC – 0.2 V or 0.2 V or open,

tRC = 125 µs, tRAS = tRAS min = 1 µs)

Unit Test

Condition

mA 1)

µA L-version

mA 2)4)

µA –

AC Characteristics 5)6)

TA = 0 to 70 ˚C, VCC = 3.3 V ± 0.3 V, tT = 2 ns

Parameter

Symbol

Limit Values

Unit Note

-50

-60

-70

min. max. min. max. min. max.

Common Parameters

Random read or write cycle time tRC

RAS precharge time

tRP

RAS pulse width

tRAS

CAS pulse width

tCAS

Row address setup time

tASR

Row address hold time

tRAH

Column address setup time

tASC

Column address hold time

tCAH

RAS to CAS delay time

tRCD

RAS to column address delay tRAD

time

89 –

104 –

124 –

ns

35 –

40 –

50 –

ns

50 10 k 60 10 k 70 10 k ns

8

10 k 10 10 k 12 10 k ns

0

–

0

–

0

–

ns

8

–

10 –

10 –

ns

0

–

0

–

0

–

ns

8

–

10 –

12 –

ns

12 37 14 45 14 53 ns

10 25 12 30 12 35 ns

Semiconductor Group

6

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