CY7C1382CV25-200AI Ver la hoja de datos (PDF) - Cypress Semiconductor

Número de pieza

componentes Descripción

Fabricante

CY7C1382CV25-200AI

512K x 36/1M x 18 Pipelined SRAM

Cypress Semiconductor 

PRELIMINARY

CY7C1380CV25

CY7C1382CV25

Pin Definitions

Name

TMS

TCK

VDD

VSS

VDDQ

VSSQ

NC

36M

72M

144M

I/O

Test Mode Select

Synchronous

JTAG serial clock

Power Supply

Ground

I/O Power Supply

I/O Ground

-

-

Description

This pin controls the Test Access Port state machine. Sampled on the

rising edge of TCK. (BGA Only)

Serial clock to the JTAG circuit. (BGA Only)

Power supply inputs to the core of the device. Should be connected to 2.5V

± 5% power supply.

Ground for the core of the device. Should be connected to ground of the

system.

Power supply for the I/O circuitry.

Ground for the I/O circuitry. Should be connected to ground of the system.

No Connects.Pins are not internally connected.

No Connects. Reserved for address expansion.

Document #: 38-05240 Rev. *A

Page 7 of 33

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