CY7C1382CV25(2004) Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C1382CV25 Datasheet PDF : 33 Pages
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CY7C1380CV25
CY7C1382CV25
CY7C1380CV25–Pin Definitions (continued)
Name
VDDQ
MODE
TDO
TDI
TMS
TCK
NC
TQFP
4,11,20,27,54,
61,70,
77
31
-
-
-
-
14,16,66,
39,38
BGA
fBGA
I/O
Description
A1,F1,J1,M1,U1, C3,C9,D3,D9,
A7,F7,J7,M7,U7 E3,E9,F3,F9,G
3,
G9,J3,J9,
K3,K9,L3,
L9,M3,M9,N3,
N9
I/O Power
Supply
Power supply for the I/O circuitry.
R3
R1
Input- Selects Burst Order. When tied to GND selects
Static
linear burst sequence. When tied to VDD or left
floating selects interleaved burst sequence.
This is a strap pin and should remain static
during device operation. Mode Pin has an
internal pull-up.
U5
P7
JTAG serial Serial data-out to the JTAG circuit. Delivers
output data on the negative edge of TCK. If the JTAG
Synchronous feature is not being utilized, this pin should be
disconnected. This pin is not available on TQFP
packages.
U3
P5
JTAG serial Serial data-In to the JTAG circuit. Sampled on
input the rising edge of TCK. If the JTAG feature is not
Synchronous being utilized, this pin can be disconnected or
connected to VDD. This pin is not available on
TQFP packages.
U2
R5
JTAG serial Serial data-In to the JTAG circuit. Sampled on
input the rising edge of TCK. If the JTAG feature is not
Synchronous being utilized, this pin can be disconnected or
connected to VDD. This pin is not available on
TQFP packages.
U4
R7
JTAG-Clock Clock input to the JTAG circuitry. If the JTAG
feature is not being utilized, this pin must be
connected to VSS. This pin is not available on
TQFP packages.
B1,C1,
A11,B1,C2,
-
No Connects. Not internally connected to the
R1,T1,T2,J3, C10,H1,H3,H9
die
D4,
,H10,
L4,J5,R5,6T, N2,N5,N7,N10
6U,
,P1,A1,B11,P2
B7,C7,
,R2,N6
R7
CY7C1382CV25–Pin Definitions
Name
A0, A1, A
TQFP
37,36,32,
33,34,35,
42,43,44,
45,46,47,
48,49,50,
80,81,82,
99,100
BWA,BWB
93,94
BGA
P4,N4,
A2,B2,
C2,R2,
T2,A3,
B3,C3,
T3,A5,
B5,C5,
T5,A6,
B6,C6,
R6,T6
G3,L5
fBGA
I/O
Description
R6,P6,A2,
A10,A11,
B2,B10,P3,P4,N6,P
8,P9,
P10,P11,
R3,R4,R8,R9,R10,
R11
Input- Address Inputs used to select one of the
Synchronous address locations. Sampled at the rising
edge of the CLK if ADSP or ADSC is active
LOW, and CE1, CE2, and CE3 are sampled
active. A1: A0 are fed to the two-bit counter..
B5,A4
Input- Byte Write Select Inputs, active LOW.
Synchronous Qualified with BWE to conduct byte writes to
the SRAM. Sampled on the rising edge of CLK.
Document #: 38-05240 Rev. *C
Page 8 of 33
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