CY7C1380CV25-167BGI(2004) Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C1380CV25-167BGI Datasheet PDF : 33 Pages
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CY7C1380CV25
CY7C1382CV25
CY7C1380CV25–Pin Definitions
Name
A0, A1, A
TQFP
37,36,32,
33,34,35,
42,43,44,45,
46,47,48,
49,50,81,
82,99,100
BWA,BWB
BWC,BWD
GW
93,94,95,
96
88
BWE
87
CLK
89
CE1
98
CE2[2]
97
CE3[2]
92
OE
86
ADV
83
ADSP
84
BGA
fBGA
I/O
Description
P4,N4,
A2,B2,
C2,R2,
A3,B3,C3,
T3,T4,A5,B5,
C5,
T5,A6,B6,C6,R6
R6,P6,A2,
Input- Address Inputs used to select one of the
A10,B2, Synchronous address locations. Sampled at the rising edge
B10,N6,P3,P4,
P8,P9,P10,
P11,R3,R4,R8,
of the CLK if ADSP or ADSC is active LOW, and
CE1, CE2, and CE3 [2]are sampled active. A1: A0
are fed to the two-bit counter..
R9,R10,R11
L5,G5,
G3,L3
H4
M4
B5,A5,A4,
B4
B7
A7
Input- Byte Write Select Inputs, active LOW.
Synchronous Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
Input- Global Write Enable Input, active LOW. When
Synchronous asserted LOW on the rising edge of CLK, a
global write is conducted (ALL bytes are written,
regardless of the values on BWX and BWE).
Input- Byte Write Enable Input, active LOW.
Synchronous Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
K4
B6
Input- Clock Input. Used to capture all synchronous
Clock inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW,
during a burst operation.
E4
A3
Input- Chip Enable 1 Input, active LOW. Sampled on
Synchronous the rising edge of CLK. Used in conjunction with
CE2 and CE3 to select/deselect the device.
ADSP is ignored if CE1 is HIGH.
-
B3
Input- Chip Enable 2 Input, active HIGH. Sampled on
Synchronous the rising edge of CLK. Used in conjunction with
CE1 and CE3 to select/deselect the device.
-
A6
Input- Chip Enable 3 Input, active LOW. Sampled on
Synchronous the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select/deselect the device.Not
available for AJ package version.Not connected
for BGA. Where referenced, CE3 is assumed
active throughout this document for BGA.
F4
B8
Input- Output Enable, asynchronous input, active
Asynchronous LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs.
When deasserted HIGH, I/O pins are
three-stated, and act as input data pins. OE is
masked during the first clock of a read cycle
when emerging from a deselected state.
G4
A9
Input- Advance Input signal, sampled on the rising
Synchronous edge of CLK, active LOW. When asserted, it
automatically increments the address in a burst
cycle.
A4
B9
Input- Address Strobe from Processor, sampled on
Synchronous the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the
device are captured in the address registers. A1:
A0 are also loaded into the burst counter. When
ADSP and ADSC are both asserted, only ADSP
is recognized. ASDP is ignored when CE1 is
deasserted HIGH.
Document #: 38-05240 Rev. *C
Page 6 of 33
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