CY7C1382CV25-167BZC(2004) Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C1382CV25-167BZC Datasheet PDF : 33 Pages
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CY7C1380CV25
CY7C1382CV25
CY7C1382CV25–Pin Definitions (continued)
Name
TMS
TCK
NC
TQFP
-
-
1,2,3,6,7,
14,16,25,
28,29,30,
38,39,
51,52,53,
56,57,66,
75,78,79,
95,96
BGA
fBGA
I/O
Description
U2
R5
JTAG serial Serial data-In to the JTAG circuit. Sampled
input on the rising edge of TCK. If the JTAG feature
Synchronous is not being utilized, this pin can be discon-
nected or connected to VDD. This pin is not
available on TQFP packages.
U4
R7
JTAG-Clock Clock input to the JTAG circuitry. If the JTAG
feature is not being utilized, this pin must be
connected to VSS. This pin is not available on
TQFP packages.
B1,B7,
A5,B1,B4,
-
No Connects. Not internally connected to the
C1,C7, C1,C2,C10,D1,D10,
die.
D2,D4,
E1,E10,F1,
D7,E1,
F10,G1,
E6,H2, G10,H1,H3,H9,H10,
F2,G1,
J2,J11,
G6,H7,
K2,
J3,J5,K1, K11,L2,L1,M2,M11,
K6,L4,L2,L7,
N2,N7,N10,
M6,
N5,
N2,L7,P1,P6,
N11,P1,A1,
R1,
B11,
R5,R7,
P2,R2
T1,T4,U6
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (tCO) is 3.0ns
(200-MHz device).
The CY7C1380CV25/CY7C1382CV25 supports secondary
cache in systems utilizing either a linear or interleaved burst
sequence. The interleaved burst order supports Pentium and
i486 processors. The linear burst sequence is suited for
processors that utilize a linear burst sequence. The burst order
is user selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the Processor
Address Strobe (ADSP) or the Controller Address Strobe
(ADSC). Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW) overrides all Byte Write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. ADSP is ignored if
CE1 is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE1, CE2, CE3 are all asserted active, and (3) the Write
signals (GW, BWE) are all deserted HIGH. ADSP is ignored if
CE1 is HIGH. The address presented to the address inputs (A)
is stored into the address advancement logic and the Address
Register while being presented to the memory array. The
corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 3.0 ns (200-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always three-stated during the first cycle of the access. After
the first cycle of the access, the outputs are controlled by the
OE signal. Consecutive single Read cycles are supported.
Once the SRAM is deselected at clock rise by the chip select
and either ADSP or ADSC signals, its output will three-state
immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) CE1, CE2, CE3 are all asserted active. The address
presented to A is loaded into the address register and the
address advancement logic while being delivered to the
memory array. The Write signals (GW, BWE, and BWX) and
ADV inputs are ignored during this first cycle.
ADSP-triggered Write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the corre-
sponding address location in the memory array. If GW is HIGH,
then the Write operation is controlled by BWE and BWX
signals. The CY7C1380CV25/CY7C1382CV25 provides Byte
Write capability that is described in the Write Cycle Descrip-
tions table. Asserting the Byte Write Enable input (BWE) with
the selected Byte Write (BWX) input, will selectively write to
only the desired bytes. Bytes not selected during a Byte Write
operation will remain unaltered. A synchronous self-timed
Document #: 38-05240 Rev. *C
Page 11 of 33
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