CY7C1382CV25-225BZC(2004) Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C1382CV25-225BZC Datasheet PDF : 33 Pages
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CY7C1380CV25
CY7C1382CV25
CY7C1382CV25–Pin Definitions (continued)
Name
ZZ
DQs,
DQPs
VDD
VSS
VSSQ
VDDQ
MODE
TDO
TDI
TQFP
BGA
fBGA
I/O
Description
64
T7
H11
Input- ZZ “sleep” Input, active HIGH. When
Asynchronou asserted HIGH places the device in a
s
non-time-critical “sleep” condition with data
integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has
an internal pull-down.
58,59,62,
63,68,69,
72,73,8,9,
12,13,18,
19,22,23,
74,24
P7,K7,
G7,E7,
F6,H6,L6,N6,
D1,
H1,L1,
N1,E2,
G2,K2,
M2,D6,
P2
J10,K10,
L10,M10,
D11,E11,
F11,G11,J1,K1,L1,M
1,D2,E2,F2,
G2,C11,N1
I/O-
Bidirectional Data I/O lines. As inputs, they
Synchronous feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs,
they deliver the data contained in the memory
location specified by the addresses presented
during the previous clock rise of the read cycle.
The direction of the pins is controlled by OE.
When OE is asserted LOW, the pins behave
as outputs. When HIGH, DQs and DQPX are
placed in a three-state condition.
15,41,65,
91
C4,J2,J4,J6,
R4
D4,D8,E4,E8,F4,F8, Power Supply Power supply inputs to the core of the
G4,G8,H4,
device.
H8,J4,J8,
K4,K8,L4,
L8,M4,M8
17,40,67,
90
D3,D5, H2,C4,C5,C6,C7,C8
E5,E3,F3,F5, ,D5,D6,D7,E5,E6,E7
G5,
,
H3,H5,
F5,F6,F7,
K3,K5,L3,M3,
G5,G6,G7,
M5,
H5,H6,H7,J5,J6,J7,
N3,N5,
K5,K6,K7,
P3,P5
L5,L6,L7,
M5,M6,M7,N4,N8
Ground
Ground for the core of the device.
5,10,21,26,55,
-
60,71,
76
-
I/O Ground Ground for the I/O circuitry.
4,11,20,27,54,
61,70,
77
A1,A7,F1,F7,
J1,J7,M1,M7,
U1,U7
C3,C9,D3,D9,E3,E9
,
F3,F9,G3,
G9,J3,J9,
K3,K9,L3,
L9,M3,M9,N3,N9
I/O Power Power supply for the I/O circuitry.
Supply
31
R3
R1
Input- Selects Burst Order. When tied to GND
Static selects linear burst sequence. When tied to
VDD or left floating selects interleaved burst
sequence. This is a strap pin and should
remain static during device operation. Mode
Pin has an internal pull-up.
-
U5
P7
JTAG serial Serial data-out to the JTAG circuit. Delivers
output data on the negative edge of TCK. If the JTAG
Synchronous feature is not being utilized, this pin should be
left unconnected. This pin is not available on
TQFP packages.
-
U3
P5
JTAG serial Serial data-In to the JTAG circuit. Sampled
input on the rising edge of TCK. If the JTAG feature
Synchronous is not being utilized, this pin can be left floating
or connected to VDD through a pull up resistor.
This pin is not available on TQFP packages.
Document #: 38-05240 Rev. *C
Page 10 of 33
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