X28C010 Ver la hoja de datos (PDF) - Xicor -> Intersil

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X28C010

5 Volt, Byte Alterable E2PROM

Xicor -> Intersil 

X28C010

The Toggle Bit I/O6

Figure 4. Toggle Bit Bus Sequence

LAST

WE WRITE

CE

OE

I/O6

VOH

*

VOL

* Beginning and ending state of I/O6 will vary.

Figure 5. Toggle Bit Software Flow

LAST WRITE

LOAD ACCUM

FROM ADDR n

COMPARE

ACCUM WITH

ADDR n

HIGH Z

*

X28C010

READY

3858 FHD F14

The Toggle Bit can eliminate the software housekeeping

chore of saving and fetching the last address and data

written to a device in order to implement DATA Polling.

This can be especially helpful in an array comprised of

multiple X28C010 memories that is frequently updated.

Toggle Bit Polling can also provide a method for status

checking in multiprocessor applications. The timing

diagram in Figure 4 illustrates the sequence of events on

the bus. The software flow diagram in Figure 5 illustrates

a method for polling the Toggle Bit.

NO

COMPARE

OK?

YES

X28C010

READY

3858 FHD F15

5

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