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HIP0045

1A/50V Octal Low Side Power Driver With Serial Bus Control and Fault Protection

Intersil 

HIP0045

Serial Peripheral Interface Timing (MOSI, MISO Load Capacitor = 100pF, See Figure 1)

PARAMETER

SYMBOL

TEST CONDITION

MIN TYP MAX UNITS

Data Valid Time, SCK to Data at MISO Valid

Time for SCK Low before CE Low (SCK Setup Time

before CE High to Low Change)

tV

VCC = 5V ±0.1V

tSCK_LEAD

-

-

100

ns

100

-

-

ns

Time for SCK High after CE High

CE Pulse Filter Time

tSCK_LAG

150

-

-

ns

-

Note 9

-

ns

NOTES:

7. The MOSFET Output Drain is internally clamped with a Drain-to-Gate zener diode that turns-on the MOSFET; holding the Drain at the Output

Clamp Voltage, VOC.

8. The measurement of Output Leakage Current includes the Output Pull-Down Current, ISK. Each Output has a Current Pull-Down which is used

to detect open load fault conditions.

9. The digital filter time for the output latch function determines if the output latch function will be enabled. The output latch function will only be

enabled if a positive CE slope occurs after 8 SCK clock cycles or a multiple of 8 SCK cycles since the last CE negative slope change.

Timing Diagrams

CE

SCK

(CPOL = 0, CPHA = 1)

MSB 6

5

4

3

2

1

LSB

INTERNAL STROBE FOR DATA CAPTURE

FIGURE 1A. DATA AND CLOCK TIMING DIAGRAM

CE

(INPUT)

tLEAD tWSCKH

SCK

(INPUT)

MISO

(OUTPUT)

HIGH

Z

LAST BIT

tWSCKL

TRANSMITTED

D7O

tEN

tV

MOSI

(INPUT)

D7I

tSU tH

D6O

D6I

DRIVER

OUTPUT

OLD

tLAG

D0O

D0I

FIGURE 1B. SPI TIMING DIAGRAM

4-5

tDIS

FAULT-INDUCED

TURN-OFF

NEW

tDON

tDOFF

tDF

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