MCP19114/5
TABLE 2: 28-PIN SUMMARY
Basic
Additional
GPA0 1 Y AN0 —
GPA1 2 Y AN1 —
—
IOC
Y
—
IOC
Y
—
Analog/Digital Debug Output(1)
—
Sync Signal In/Out(2)
GPA2 3 Y AN2 T0CKI —
IOC
Y
—
—
INT
GPA3 5 Y AN3 —
—
IOC
Y
—
—
GPA5
8N
—
—
—
IOC(4) Y(5)
MCLR
Test Enable Input
GPA6
7N
—
—
—
IOC
Y
—
Dual Capture/Single
Compare1 Input
GPA7
6N
—
—
SCL IOC
N
—
—
GPB0 10 N
—
—
SDA IOC
N
—
GPB1 26 Y AN4 —
—
IOC
Y
—
GPB4 4 Y AN5 —
—
IOC
Y
ICSPDAT
—
VREF2(3)
—
GPB5 27 Y AN6 —
—
IOC
Y
ICSPCLK
—
GPB6 28 Y AN7 —
—
IOC
Y
—
—
GPB7
9Y
—
—
—
IOC
Y
—
Single Compare2 Input
DESATP/ 12 N
—
—
—
—
—
—
ISOUT
DESATN 11 N
—
—
—
—
—
—
ISP
13 N
—
—
—
—
Y
—
DESATP input or ISOUT
Output(6)
DESAT Negative Input
Current Sense Amplifier
Noninverting Input
ISN
14 N
—
—
—
—
—
—
Current Sense Amplifier
Inverting Input
IP
15 N
—
—
—
—
—
AGND
16 N
—
—
—
—
—
PGND
17 N
—
—
—
—
—
SDRV 18 N
—
—
—
—
—
—
AGND
PGND
—
Primary Input Current Sense
Small Signal Ground
Large Signal Ground
Secondary LS Gate Drive
Output
PDRV 19 N
—
—
—
—
—
—
Primary LS Gate Drive Output
VDR
VDD
VIN
VS
IFB
ICOMP
Note 1:
20 N
—
—
—
—
—
21 N
—
—
—
—
—
22 N
—
—
—
—
—
23 N
—
—
—
—
—
VDR
Gate Drive Supply Voltage
VDD
VDD Output
VIN
Input Supply Voltage
—
Output Voltage Sense
24 N
—
—
—
—
—
—
Error Amplifier Feedback input
25 N
—
—
—
—
—
—
Error Amplifier Output
The Analog/Digital Debug Output is selected through the control of the ABECON register.
2: Selected when functioning as master or slave by proper configuration of the MSC<1:0> bits in the
MODECON register.
3: VREF2 output selected when configured as master by proper configuration of the MSC<1:0> bits in the
MODECON register.
4: The IOC is disabled when MCLR is enabled.
5: Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control.
6: When RFB of MODECON<6> = 0, the internal feedback resistor is enabled allow with DESATP input.
When RFB = 1, ISOUT is enabled.
2014-2015 Microchip Technology Inc.
DS20005281B-page 5