MCP19114/5
TABLE 1: 24-PIN SUMMARY
Basic
Additional
GPA0 1 Y AN0 —
GPA1 2 Y AN1 —
—
IOC
Y
—
IOC
Y
—
Analog/Digital Debug Output(1)
—
Sync Signal In/Out(2)
GPA2 3 Y AN2 T0CKI —
IOC
Y
—
—
INT
GPA3 4 Y AN3 —
—
IOC
Y
—
—
GPA5
7N
—
—
—
IOC(4) Y(5)
MCLR
Test Enable Input
GPA6
6N
—
—
—
IOC
Y ICSPDAT Dual Capture/Compare Input
GPA7
5N
—
—
SCL IOC
N ICSPCLK
—
GPB0 8 N
—
—
SDA IOC
N
GPB1 24 Y AN4 —
—
IOC
Y
DESATN 9 N
—
—
—
—
—
DESATP/ 10 N
—
—
—
—
—
ISOUT
ISP
11 N
—
—
—
—
Y
—
—
—
VREF2(3)
—
DESAT Negative Input
—
DESATP Input or ISOUT
Output(6)
—
Current Sense Amplifier Positive
Input
ISN
12 N
—
—
—
—
—
—
Current Sense Amplifier
Negative Input
IP
13 N
—
—
—
—
—
—
Primary Input Current Sense
AGND
14 N
—
—
—
—
—
AGND
Small Signal Ground
PGND
15 N
—
—
—
—
—
PGND
Large Signal Ground
SDRV 16 N
—
—
—
—
—
—
Secondary LS Gate Drive
Output
PDRV 17 N
—
—
—
—
—
—
Primary LS Gate Drive
Output
VDR
VDD
VIN
VS
IFB
ICOMP
Note 1:
18 N
—
—
—
—
—
VDR
19 N
—
—
—
—
—
VDD
20 N
—
—
—
—
—
VIN
21 N
—
—
—
—
—
—
Gate Drive Supply Voltage
VDD Output
Input Supply Voltage
Output Voltage Sense
22 N
—
—
—
—
—
—
Error Amplifier Feedback Input
23 N
—
—
—
—
—
—
Error Amplifier Output
The Analog/Digital Debug Output is selected through the control of the ABECON register.
2: Selected when functioning as master or slave by proper configuration of the MSC<1:0> bits in the
MODECON register.
3: VREF2 output selected when configured as master by proper configuration of the MSC<1:0> bits in the
MODECON register.
4: The IOC is disabled when MCLR is enabled.
5: Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control.
6: When RFB of MODECON<5> = 0, the internal feedback resistor and DESATP input are enabled. When
RFB = 1, ISOUT is enabled.
2014-2015 Microchip Technology Inc.
DS20005281B-page 3