S3C6410 Ver la hoja de datos (PDF) - Samsung

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componentes Descripción

Fabricante

S3C6410

RISC Microprocessor

Samsung 

Table of Contents (Continued)

Chapter 4

Memory Sub-system

4.1. Overview................................................................................................................................................. 4-1

4.2. Introduction ............................................................................................................................................. 4-1

4.3. Structure ................................................................................................................................................. 4-2

4.4. AHB slave interface (SFR) ..................................................................................................................... 4-2

4.5. AHB slave interface (SPINE).................................................................................................................. 4-3

4.6. EBI Multiplexing ...................................................................................................................................... 4-5

4.7. Configuration Options............................................................................................................................. 4-7

4.8. Use of wide address spaces for SROM Controller (Using dram 1 PORT) ............................................ 4-8

4.9. Sharing Chip Select for memory port 0 .................................................................................................. 4-9

4.10.Remapping............................................................................................................................................ 4-15

4.11.Address decoding ................................................................................................................................. 4-16

Chapter 5

DRAM Controller

5.1 Overview ................................................................................................................................................. 5-1

5.2 Features .................................................................................................................................................. 5-2

5.3 SDRAM Memory interface ...................................................................................................................... 5-3

5.4 SDRAM Initialization Sequence .............................................................................................................. 5-4

5.4.1 DRAM Controller Initialization Sequence ........................................................................................ 5-4

5.4.2 SDR/mobile SDR SDRAM Initialization Sequence.......................................................................... 5-4

5.4.3 DDR/mobile DDR SDRAM Initialization Sequence ......................................................................... 5-4

5.5 Register Description................................................................................................................................ 5-5

5.5.1 DRAM Controller Status Register.................................................................................................... 5-5

5.5.2 DRAM Controller Command Register ...........htt.p://ww.w.Da.taShe.et4U..net/ ............................................................................. 5-5

5.5.3 Direct Command Register ............................................................................................................... 5-6

5.5.4 Memory Configuration Register....................................................................................................... 5-7

5.5.5 Refresh Period Register .................................................................................................................. 5-8

5.5.6 CAS Latency Register ..................................................................................................................... 5-8

5.5.7 T_DQSS Register ............................................................................................................................ 5-9

5.5.8 T_MRD Register .............................................................................................................................. 5-9

5.5.9 T_RAS Register............................................................................................................................... 5-9

5.5.10 T_RC Register ............................................................................................................................... 5-10

5.5.11 T_RCD Register ............................................................................................................................ 5-10

5.5.12 T_RFC Register............................................................................................................................. 5-10

5.5.13 T_RP Register ............................................................................................................................... 5-10

5.5.14 T_RRD Register ............................................................................................................................ 5-11

5.5.15 T_WR Register .............................................................................................................................. 5-11

5.5.16 T_WTR Register ............................................................................................................................ 5-11

5.5.17 T_XP Register ............................................................................................................................... 5-12

5.5.18 T_XSR Register............................................................................................................................. 5-12

5.5.19 T_ESR Register............................................................................................................................. 5-12

5.5.20 Memory configuration 2 register .................................................................................................... 5-13

5.5.21 Memory configuration 3 register .................................................................................................... 5-14

5.5.22 ID_N_CFG Register ...................................................................................................................... 5-14

5.5.23 CHIP_N_CFG Register ................................................................................................................. 5-15

5.5.24 USER_STATUS Register .............................................................................................................. 5-16

5.5.25 USER_CONFIG Register .............................................................................................................. 5-16

S3C6410X_USER’S MANUAL_REV 1.10

vii

datasheet pdf - http://www.DataSheet4U.net/

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