S3C6410 Ver la hoja de datos (PDF) - Samsung

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componentes Descripción

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S3C6410

RISC Microprocessor

Samsung 

Table of Contents (Continued)

Chapter 15 Post Processor

15.1 Overview................................................................................................................................................15-1

15.2 Features ................................................................................................................................................15-2

15.3 A Source and Destination Image Data Format .....................................................................................15-3

15.3.1 DMA Mode Operation ....................................................................................................................15-4

15.3.2 FIFO Mode Operation ....................................................................................................................15-7

15.4 Image Size and Scale Ratio ..................................................................................................................15-7

15.5 DMA operation of Source and Destination Image.................................................................................15-9

15.5.1 Start address..................................................................................................................................15-10

15.5.2 End address ...................................................................................................................................15-10

15.6 Frame Management of POST Processor..............................................................................................15-12

15.6.1 Per Frame Management Mode ......................................................................................................15-12

15.6.2 Free Run Mode ..............................................................................................................................15-12

15.7 Register File Lists..................................................................................................................................15-13

15.7.1 MODE Control Register .................................................................................................................15-15

15.7.3 Pre-Scale Image Size Register......................................................................................................15-17

15.7.4 Source Image Size Register ..........................................................................................................15-18

15.7.5 Horizontal Main Scale Ratio Register ............................................................................................15-18

15.7.6 Vertical Main Scale Ratio Register ................................................................................................15-18

15.7.7 Destination Image Size Register ...................................................................................................15-19

15.7.8 Pre-Scale Shift Factor Register .....................................................................................................15-19

15.7.9 DMA Start Address Register..........................................................................................................20

15.7.10 DMA End Address Register .........................................................................................................15-21

15.7.11 Current Frame(Buffer0) and Next Frame(Buffer1) http://www.DataSheet4U.net/ Offset Register .............................................15-22

15.7.12 Next Frame DMA Start Address Register....................................................................................15-23

15.7.13 Next Frame DMA End Address Register .....................................................................................15-24

15.7.14 DMA Start address Register for Output Cb and Cr .....................................................................15-24

15.7.15 DMA End Address Register for Output Cb and Cr ......................................................................15-25

15.7.16 Current Frame(Buffer0) and Next Frame(Buffer1) Offset Register for Output Cb and Cr ..........15-25

15.7.17 15.26 Next Frame DMA Start Address Register for Output Cb and Cr .......................................15-25

15.7.18 Next Frame DMA End Address Register for Output Cb and Cr ..................................................15-26

15.7.19 POSTENVID Register to Enable Video Processing ....................................................................15-26

15.7.20 MODE Control Register 2 ............................................................................................................15-27

xviii

S3C6410X_USER’S MANUAL_REV 1.00

datasheet pdf - http://www.DataSheet4U.net/

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