BH1750FVI Ver la hoja de datos (PDF) - ROHM Semiconductor
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BH1750FVI
ROHM Semiconductor
BH1750FVI Datasheet PDF : 18 Pages
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BH1750FVI
Technical Note
●Application circuit example of DVI terminal
The DVI terminal is an asynchronous reset terminal. Please note that there is a possibility that IC doesn't operate normally
if the reset section is not installed after the start-up of VCC.
(Please refer to the paragraph of "Timing chart for VCC and DVI power supply sequence" )
The description concerning SDA and the terminal SCL is omitted in this application circuit example. Please design the
application the standard of the I2C bus as it finishes being satisfactory. Moreover, the description concerning the terminal
ADDR is omitted. Please refer to the paragraph of "Timing chart for VCC and DVI power supply sequence" about the terminal
ADDR design.
ex 1) The control signal line such as CPU is connected.
BH1750FVI
0.1µF
VCC
ADDR
GND
SCL
DVI
SDA
0.1µF
Micro
Controller
ex 2) Reset IC is used.
1, For Reset IC of the Push-Pull type
0.1µF
BH1750FVI
VCC
SCL
ADDR
DVI
GND
SDA
0.1µF
RESET
Reset IC( Push-Pull type )
2, For Reset IC of the Open drain output
0.1µF
BH1750FVI
VCC
SCL
ADDR
DVI
GND
SDA
1kOhm
0.1µF
RESET
Reset IC( Open drain type )
ex 3) A different power supply is used.
BH1750FVI
0.1µF
VCC
V1
ADDR
GND
SCL
DVI
SDA
V2
0.1µF
※ Power supply of DVI must stand up later than power supply of VCC stand up, because it is necessary to secure reset section ( 1µs or more ).
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8/17
2011.11 - Rev.D
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