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BH1750FVI(2009) Ver la hoja de datos (PDF) - ROHM Semiconductor

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BH1750FVI
Technical Note
Timing chart for VCC and DVI power supply sequence
DVI is I2C bus reference voltage terminal. And it is also asynchronous reset terminal. It is necessary to set to 'L' after VCC is
supplied. In DVI 'L' term, internal state is set to Power Down mode.
1) Recommended Timing chart1 for VCC and DVI supply.
VCC
DVI
Reset Term ( more than 1us )
2) Timing chart2 for VCC and DVI supply.
( If DVI rises within 1µs after VCC supply )
VCC
DVI
Reset Term ( more than 1us )
Don't care state
ADDR, SDA, SCL is not stable if DVI 'L' term ( 1us ) is not given by systems.
In this case, please connect the resisters ( approximately 100kOhm ) to ADDR without directly
connecting to VCC or GND,
because it is 3 state buffer for Internal testing.
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© 2009 ROHM Co., Ltd. All rights reserved.
6/17
2009.04- Rev.B

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