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BH1750FVI(2009) Ver la hoja de datos (PDF) - ROHM Semiconductor

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BH1750FVI Datasheet PDF : 18 Pages
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BH1750FVI
Technical Note
I2C Bus Access
1 ) I2C Bus Interface Timing chart
Write measurement command and Read measurement result are done by I2C Bus interface. Please refer the formally
specification of I2C Bus interface, and follow the formally timing chart.
SDA
tf
tLOW
tr
tSU ; DAT
tf
SCL
tHD ; STA
S
tHD ; DAT
tHtIGH
tSU ; STA
Sr
S
2) Slave Address
Slave Address is 2 types, it is determined by ADDR Terminal
ADDR = ‘H’ ( ADDR 0.7VCC ) “1011100“
ADDR = 'L' ( ADDR 0.3VCC ) “0100011“
tHtHD ;DSTA
tr
tBUF
tSU;STO
P
SS
3 ) Write Format
BH1750FVI is not able to accept plural command without stop condition. Please insert SP every 1 Opecode.
ST
Slave Address
R/W
0
Ack
Opecode
Ack SP
4 ) Read Format
ST
Slave Address
R/W
1
Ack
High Byte [15:8]
215 214 213 212 211 210 29 28
Ack
Low Byte [7:0]
27 26 25 24 23 22 21 20
Ack SP
from Master to Slave
ex )
High Byte = "1000_0011"
Low Byte = "1001_0000"
( 215 + 29 + 28 + 27 + 24 ) / 1.2 28067 [ lx ]
* I2C BUS is trademark of Phillips Semiconductors. Please refer formality specification.
from Slave to Master
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
10/17
2009.04- Rev.B

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