ADE7758(2004) Ver la hoja de datos (PDF) - Analog Devices

Número de pieza

componentes Descripción

Fabricante

ADE7758
(Rev.:2004)

Poly Phase Multifunction Energy Metering IC with Per Phase Information

Analog Devices 

ADE7758

TIMING CHARACTERISTICS1, 2

AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 10 MHz XTAL, TMIN to TMAX = −40°C to +85°C.

Table 2.

Parameter

Write Timing

t1

t2

t3

t4

t5

t6

t7

t8

Read Timing

t9

t10

t113

t124

t134

Specification Unit

50

ns (min)

50

ns (min)

50

ns (min)

10

ns (min)

5

ns (min)

900

ns (min)

50

ns (min)

100

ns (min)

1.1

µs (min)

50

ns (min)

30

ns (min)

100

ns (max)

10

ns (min)

100

ns (max)

10

ns (min)

Test Conditions/Comments

CS falling edge to first SCLK falling edge.

SCLK logic high pulse width.

SCLK logic low pulse width.

Valid data setup time before falling edge of SCLK.

Data hold time after SCLK falling edge.

Minimum time between the end of data byte transfers.

Minimum time between byte transfers during a serial write.

CS hold time after SCLK falling edge.

Minimum time between read command (i.e., a write to communication register) and data read.

Minimum time between data byte transfers during a multibyte read.

Data access time after SCLK rising edge following a write to the communications register.

Bus relinquish time after falling edge of SCLK.

Bus relinquish time after rising edge of CS.

1 Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns

(10% to 90%) and timed from a voltage level of 1.6 V.

2 See the timing diagrams in Figure 3 and Figure 4 and the ADE7758 Serial Interface section.

3 Measured with the load circuit in Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.

4 Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated back

to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of

the part and is independent of the bus loading.

200µA

IOL

TO OUTPUT

PIN CL

50pF

1.6mA

IOH

2.1V

Figure 2. Load Circuit for Timing Specifications

Rev. A | Page 7 of 68

Share Link: