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AZC002-02N

Low Capacitance ESD Protection Array For High Speed Data Interfaces

Amazing Microelectronic 

AZC002-02N

Low Capacitance ESD Protection Array

For High Speed Data Interfaces

B. Device Connection

The AZC002-02N is designed to protect two

data lines and power rails from transient

over-voltage (such as ESD stress pulse). The

device connection of AZC002-02N is shown in

the Fig. 2. In Fig. 2, the two protected data lines

are connected to the ESD protection pins (pin2

and pin3) of AZC002-02N. The ground pin (pin1)

of AZC002-02N is a negative reference pin. This

pin should be directly connected to the GND rail

of PCB (Printed Circuit Board). To get minimum

parasitic inductance, the path length should keep

as short as possible. In addition, the power pin

(pin 4) of AZC002-02N is a positive reference pin.

This pin should directly connect to the VDD rail of

PCB. When pin 4 of AZC002-02N is connected to

the VDD rail, the leakage current of ESD

protection pin of AZC002-02N becomes very

small. Because the pin 4 of AZC002-02N is

directly connected to VDD rail, the VDD rail also

can be protected by the power-rail ESD clamped

circuit (not shown) of AZC002-02N.

AZC002-02N can provide protection for 2 I/O

signal lines simultaneously. If the number of I/O

signal lines is less than 2, the unused I/O pins

can be simply left as NC pins.

In some cases, systems are not allowed

to be reset or restart after the ESD stress

directly applying at the I/O-port connector.

Under this situation, in order to enhance the

sustainable ESD Level, a 0.1µF chip capacitor

can be added between the VDD and GND rails.

The place of this chip capacitor should be as

close as possible to the AZC002-02N.

GND rail

1

VDD rail

4

*Optional

0.1µF

Chip Cap.

2

3

I/O 1

To

I/O-port

Conne ctor

I/O 2

data line

data line

I/O 1 To

Prote cte d

IC

I/O 2

Fig. 2 Data lines and power rails connection of AZC002-02N.

Revision 2011/07/30 ©2011-2012 Amazing Micro.

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