SST27SF010-70-3C-WG Ver la hoja de datos (PDF) - Silicon Storage Technology
Número de pieza
componentes Descripción
Fabricante
SST27SF010-70-3C-WG
Silicon Storage Technology
SST27SF010-70-3C-WG Datasheet PDF : 23 Pages
| |||
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash
SST27SF512 / SST27SF010 / SST27SF020
Data Sheet
SST27SF512
SST27SF512
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
28
2
27
3
26
4
25
5
24
6 28-pin 23
7
PDIP 22
8 Top View 21
9
20
10
19
11
18
12
17
13
16
14
15
VDD
A14
A13
A8
A9
A11
OE#/VPP
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
1152 28-pdip P3.2
SST27SF020 SST27SF010
SST27SF010 SST27SF020
VPP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
VPP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
32
2
31
3
30
4
29
5
28
6 32-pin 27
7 PDIP 26
8 Top View 25
9
24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
VDD
PGM#
NC
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VDD
PGM#
A17
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
1152 32-pdip P4.1
FIGURE 3: PIN ASSIGNMENTS FOR 28-PIN AND 32-PIN PDIP
TABLE 2: PIN DESCRIPTION
Symbol
Pin Name
Functions
AMS1-A0
DQ7-DQ0
Address Inputs
Data Input/output
To provide memory addresses
To output data during Read cycles and receive input data during Program cycles
The outputs are in tri-state when OE# or CE# is high.
CE#
Chip Enable
To activate the device when CE# is low
OE#
Output Enable
For SST27SF010/020, to gate the data output buffers during Read operation
OE#/VPP
Output Enable/VPP For SST27SF512, to gate the data output buffers during Read operation and high voltage
pin during Chip-Erase and programming operation
VPP
Power Supply for For SST27SF010/020, high voltage pin during Chip-Erase and programming operation
Program or Erase 11.4-12V
VDD
Power Supply
To provide 5.0V supply (4.5-5.5V)
VSS
Ground
NC
No Connection
Unconnected pins.
1. AMS = Most significant address
AMS = A15 for SST27SF512, A16 for SST27SF010, and A17 for SST27SF020
T2.4 1152
©2005 Silicon Storage Technology, Inc.
5
S71152-11-000
9/05
Share Link: